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dgisselq |
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##
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## Filename: rtl/Makefile
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##
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## Project: A Wishbone Controlled PWM (audio) controller
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##
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## Purpose: To direct the Verilator build of the PWM example demo sources.
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## The result is C++ code (built by Verilator), that is then built
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## (herein) into an executable library.
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##
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## Targets: The default target, all, builds the target test, which includes
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## the libraries necessary for Verilator testing. It also builds
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## the pdmdemo target--building a C++ program which can be used to drive
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## this test via Verilator.
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2017, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program. (It's in the $(ROOT)/doc directory. Run make with no
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## target there if the PDF file isn't present.) If not, see
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## for a copy.
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##
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## License: GPL, v3, as defined and found on www.gnu.org,
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## http://www.gnu.org/licenses/gpl.html
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##
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################################################################################
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##
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##
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all: test pdmdemo
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FBDIR := .
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VDIRFB:= $(FBDIR)/obj_dir
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.PHONY: test
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test: $(VDIRFB)/Vtoplevel__ALL.a
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VOBJ := obj_dir
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SUBMAKE := $(MAKE) --no-print-directory --directory=$(VOBJ) -f
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ifeq ($(VERILATOR_ROOT),)
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VERILATOR := verilator
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VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
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else
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VERILATOR := $(VERILATOR_ROOT)/bin/verilator
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endif
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export $(VERILATOR)
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VROOT := $(VERILATOR_ROOT)
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VINCD := $(VROOT)/include
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VINC := -I$(VINCD) -I$(VINCD)/vlstd -I$(VDIRFB)
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VFLAGS := -Wall -MMD --trace -y ../rtl -cc
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$(VDIRFB)/Vtoplevel__ALL.a: $(VDIRFB)/Vcordic.h $(VDIRFB)/Vcordic.cpp
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$(VDIRFB)/Vtoplevel__ALL.a: $(VDIRFB)/Vcordic.mk
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$(VDIRFB)/Vtoplevel.h $(VDIRFB)/Vtoplevel.cpp $(VDIRFB)/Vtoplevel.mk: toplevel.v
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$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
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$(VERILATOR) $(VFLAGS) $*.v
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$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
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$(SUBMAKE) V$*.mk
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.PHONY: clean
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clean:
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rm -rf $(VDIRFB)/
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pdmdemo: pdmdemo.cpp $(VDIRFB)/Vtoplevel__ALL.a
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g++ -Wall $(VINC) $(VINCD)/verilated.cpp $(VINCD)/verilated_vcd_c.cpp $^ -o pdmdemo
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#
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# Note Verilator's dependency created information, and include it here if we
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# can
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DEPS := $(wildcard $(VDIRFB)/*.d)
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ifneq ($(DEPS),)
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include $(DEPS)
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endif
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