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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// fm_3d_fmul.v
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//
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// Abstract:
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// floating point multiplyer, latency = 3
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//
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// Author:
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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module fm_3d_fmul (
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clk_core,
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i_en,
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i_a,
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i_b,
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o_c
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);
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///////////////////////////////////////////
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// port definition
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///////////////////////////////////////////
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input clk_core;
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input i_en;
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input [21:0] i_a;
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input [21:0] i_b;
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output [21:0] o_c;
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///////////////////////////////////////////
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// register
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///////////////////////////////////////////
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reg [21:0] r_c;
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reg r_sign_1z;
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reg r_sign_2z;
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reg [17:0] r_cf_tmp;
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reg [4:0] r_ce_tmp_1z;
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reg [4:0] r_ce_tmp_2z;
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reg [16:0] r_cf_tmp2;
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///////////////////////////////////////////
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// wire definition
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///////////////////////////////////////////
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// input data separation
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wire w_a_sign;
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wire [15:0] w_a_fraction;
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wire [4:0] w_a_exp;
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wire w_b_sign;
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wire [15:0] w_b_fraction;
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wire [4:0] w_b_exp;
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// intermidiate wire
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wire [5:0] w_adder_out; // result of exp addition
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wire w_sign;
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wire [31:0] w_cf_tmp; // multplyer out 1.15 * 1.15 = 2.30
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wire [16:0] w_cf_tmp2; // multplyer out (rounded) 2.15
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wire [4:0] w_ce_tmp; // temporary exp out
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wire [21:0] w_c;
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///////////////////////////////////////////
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// stage0
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///////////////////////////////////////////
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// separate input and add implied fraction msb
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assign w_a_sign = i_a[21];
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assign w_a_exp = i_a[20:16];
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assign w_a_fraction = i_a[15:0];
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assign w_b_sign = i_b[21];
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assign w_b_exp = i_b[20:16];
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assign w_b_fraction = i_b[15:0];
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// exponent calculation
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// (ea + eb - bias)
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wire [5:0] w_exp_add;
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assign w_exp_add = w_a_exp + w_b_exp;
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assign w_adder_out = w_exp_add - 4'hf;
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assign w_ce_tmp = (w_exp_add < 5'hf) ? 5'h00 :
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(w_adder_out[5]) ? 5'h1f :
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w_adder_out[4:0];
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assign w_sign = w_a_sign ^ w_b_sign;
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// fraction multiplyer
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assign w_cf_tmp = w_a_fraction * w_b_fraction;
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///////////////////////////////////////////
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// stage1
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///////////////////////////////////////////
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always @(posedge clk_core) begin
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if (i_en) begin
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r_sign_1z <= w_sign;
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r_cf_tmp <= w_cf_tmp[31:14];
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r_ce_tmp_1z <= w_ce_tmp;
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end
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end
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// round
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//assign w_cf_tmp2 = w_cf_tmp[14] ? w_cf_tmp[31:15] + 1'b1 :
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// w_cf_tmp[31:15];
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wire [16:0] w_rounded;
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assign w_rounded = r_cf_tmp[17:1] + 1'b1;
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assign w_cf_tmp2 = r_cf_tmp[0] ? w_rounded : // 2.15
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r_cf_tmp[17:1];
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///////////////////////////////////////////
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// stage2
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///////////////////////////////////////////
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always @(posedge clk_core) begin
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if (i_en) begin
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r_sign_2z <= r_sign_1z;
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r_ce_tmp_2z <= r_ce_tmp_1z;
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r_cf_tmp2 <= w_cf_tmp2;
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end
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end
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// normalize
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fm_3d_norm norm (
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.i_s(r_sign_2z),
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.i_e(r_ce_tmp_2z),
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.i_f(r_cf_tmp2),
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.o_b(w_c)
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);
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///////////////////////////////////////////
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// stage3
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///////////////////////////////////////////
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// final register
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always @(posedge clk_core) begin
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if (i_en) r_c <= w_c;
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end
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// output port connection
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assign o_c = r_c;
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endmodule
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