URL https://opencores.org/ocsvn/wiegand_ctl/wiegand_ctl/trunk

Subversion Repositories wiegand_ctl

[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [iseconfig/] [wiegand_tx_top.projectmgr] - Blame information for rev 17

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         2
         /Automatic `includes
         /wiegand_tx_top C:|Users|jeffA|Desktop|rtl|wiegand|trunk|rtl|verilog|wiegand_tx_top.v
      
      
         wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)
      
      0
      0
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      true
      wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
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      false
      fifos.v
   
   
      
         1
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      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
      false
      work
   
   
      
         1
         Configure Target Device
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         Implement Design
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000
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   000000ff00000000000000020000011b0000011b01000000050100000002
   Implementation


Line No.	Rev	Author	Line
1	17	jeaander
2
3
4
5
6
7
8
9			`2`
10			/Automatic `includes
11			`/wiegand_tx_top C:\|Users\|jeffA\|Desktop\|rtl\|wiegand\|trunk\|rtl\|verilog\|wiegand_tx_top.v`
12
13
14			`wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)`
15
16			`0`
17			`0`
18			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010c000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010c0000000100000003000000000000000100000003`
19			`true`
20			`wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)`
21
22
23
24			`1`
25			`Design Utilities`
26
27
28
29
30			`0`
31			`0`
32			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
33			`false`
34
35
36
37
38			`1`
39
40
41			`0`
42			`0`
43			`000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001c20000000100000000`
44			`false`
45			`fifos.v`
46
47
48
49			`1`
50			`work`
51
52
53			`0`
54			`0`
55			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000`
56			`false`
57			`work`
58
59
60
61			`1`
62			`Configure Target Device`
63			`Design Utilities`
64			`Implement Design`
65
66
67			`Implement Design`
68
69			`0`
70			`0`
71			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000`
72			`false`
73			`Implement Design`
74
75			`000000ff00000000000000020000011b0000011b01000000050100000002`
76			`Implementation`
77

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Subversion Repositories wiegand_ctl

[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [iseconfig/] [wiegand_tx_top.projectmgr] - Blame information for rev 17