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[/] [wishbone_uart_controller/] [branches/] [uartcontroller/] [IOALU.vhd] - Blame information for rev 3

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--deze modulle/testbench is gemaakt door boris smidt.
--voor deze modulles kan je geen punten verdienen
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IOALU is
    Port (
                          ACK_I:  in  std_logic; --The acknowledge input 
           ADR_O:  out std_logic_vector( 7  downto 0 ):=X"00"; --adres output
           CLK_I:  in  std_logic;--clock input
           CYC_O:  out std_logic;-- The cycle output dient voor block doorvoer
 
                          DAT_I:  in  std_logic_vector( 7 downto 0 );--data in
           DAT_O:  out std_logic_vector( 7 downto 0 );--data out
           RST_I:  in  std_logic;--reset in
           --SEL_O:  out std_logic;--deze input dient voor het selecteren van de poort word echter niet gebruikt als er maar met 8 bit word gewerkt
           STB_O:   out std_logic;--The strobe output
           WE_O :       out std_logic;--write enable output 0 is read 1 is write
 
 
                          enable : in std_logic;
                          adress  : in  STD_LOGIC_VECTOR (7 downto 0);
 
                          db_in  : in  STD_LOGIC_VECTOR (7 downto 0);
                          db_out  : out  STD_LOGIC_VECTOR (7 downto 0);
 
                          rs232_we: out STD_LOGIC;
                          queue_ack: in  STD_LOGIC;
 
           opcode  : in  STD_LOGIC;
                          error  : out  STD_LOGIC;
 
                          next_instructie: out std_logic:='1');
end IOALU;
 
architecture Behavioral of IOALU is
type state is(AdressOut, readwrite,toqueue);
signal currentstate :state :=AdressOut;
signal timeout :integer range 0 to 7 := 0;
signal enable_int: std_logic := '0';
begin
process(CLK_I)
 
begin
if rising_edge(CLK_I) then
        if RST_I='1' then
                null;
        else
 
                if enable ='1' then
                        enable_int<='1';
                end if;
                if enable_int='1' then
                if opcode='0' then
                        if AdressOut = currentstate  then
                                next_instructie<='0';
                                ADR_O<=adress;
                                CYC_O<='1';
                                WE_O <='0';
                                STB_O<='1';
                                currentstate<=readwrite;
                                timeout<=0;
                        elsif currentstate=readwrite then
                                if ACK_I='1' then
                                        CYC_O<='0';
                                        WE_O <='0';
                                        STB_O<='0';
                                        ADR_O<="00000000";
                                        currentstate<=toqueue;
                                        db_out<=DAT_I;
                                        rs232_we<='1';
                                        timeout<=0;
                                elsif timeout=7 then
                                        CYC_O<='0';
                                        WE_O <='0';
                                        STB_O<='0';
                                        ADR_O<="00000000";
                                        next_instructie<='1';
                                        currentstate<=AdressOut;
                                        error<='1';
                                        timeout<=0;
                                else
                                        timeout<=timeout+1;
                                end if;
 
                        elsif currentstate=toqueue then
                                if queue_ack='1' then
                                        rs232_we<='0';
                                        next_instructie<='1';
                                        currentstate<=AdressOut;
                                        enable_int<='0';
                                end if;
                        end if;
 
 
        --------------------------------write
                else
                        if AdressOut =currentstate  then
                                next_instructie<='0';
                                ADR_O<=adress;
                                DAT_O<=db_in;
                                CYC_O<='1';
                                WE_O <='1';
                                STB_O<='1';
                                currentstate<=readwrite;
                                timeout<=0;
                        elsif currentstate=readwrite then
                                if ACK_I='1' then
                                        CYC_O<='0';
                                        WE_O <='0';
                                        STB_O<='0';
                                        currentstate<=AdressOut;
                                        ADR_O<="00000000";
                                        next_instructie<='1';
                                        timeout<=0;
                                        enable_int<='0';
                                elsif timeout=7 then
                                        CYC_O<='0';
                                        WE_O <='0';
                                        STB_O<='0';
                                        ADR_O<="00000000";
                                        currentstate<=AdressOut;
                                        error<='1';
                                        timeout<=0;
                                        enable_int<='0';
                                        next_instructie<='1';
                                else
                                        timeout<=timeout+1;
                                end if ;
                        end if;
                end if;
                end if;
        end if;
end if;
end process;
end Behavioral;
 

Line No.	Rev	Author	Line
1	3	themassau	`--deze modulle/testbench is gemaakt door boris smidt.`
2			`--voor deze modulles kan je geen punten verdienen`
3			`library IEEE;`
4			`use IEEE.STD_LOGIC_1164.ALL;`
5
6			`-- Uncomment the following library declaration if using`
7			`-- arithmetic functions with Signed or Unsigned values`
8			`use IEEE.NUMERIC_STD.ALL;`
9
10			`-- Uncomment the following library declaration if instantiating`
11			`-- any Xilinx primitives in this code.`
12			`--library UNISIM;`
13			`--use UNISIM.VComponents.all;`
14
15			`entity IOALU is`
16			`Port (`
17			`ACK_I: in std_logic; --The acknowledge input`
18			`ADR_O: out std_logic_vector( 7 downto 0 ):=X"00"; --adres output`
19			`CLK_I: in std_logic;--clock input`
20			`CYC_O: out std_logic;-- The cycle output dient voor block doorvoer`
21
22			`DAT_I: in std_logic_vector( 7 downto 0 );--data in`
23			`DAT_O: out std_logic_vector( 7 downto 0 );--data out`
24			`RST_I: in std_logic;--reset in`
25			`--SEL_O: out std_logic;--deze input dient voor het selecteren van de poort word echter niet gebruikt als er maar met 8 bit word gewerkt`
26			`STB_O: out std_logic;--The strobe output`
27			`WE_O : out std_logic;--write enable output 0 is read 1 is write`
28
29
30			`enable : in std_logic;`
31			`adress : in STD_LOGIC_VECTOR (7 downto 0);`
32
33			`db_in : in STD_LOGIC_VECTOR (7 downto 0);`
34			`db_out : out STD_LOGIC_VECTOR (7 downto 0);`
35
36			`rs232_we: out STD_LOGIC;`
37			`queue_ack: in STD_LOGIC;`
38
39			`opcode : in STD_LOGIC;`
40			`error : out STD_LOGIC;`
41
42			`next_instructie: out std_logic:='1');`
43			`end IOALU;`
44
45			`architecture Behavioral of IOALU is`
46			`type state is(AdressOut, readwrite,toqueue);`
47			`signal currentstate :state :=AdressOut;`
48			`signal timeout :integer range 0 to 7 := 0;`
49			`signal enable_int: std_logic := '0';`
50			`begin`
51			`process(CLK_I)`
52
53			`begin`
54			`if rising_edge(CLK_I) then`
55			`if RST_I='1' then`
56			`null;`
57			`else`
58
59			`if enable ='1' then`
60			`enable_int<='1';`
61			`end if;`
62			`if enable_int='1' then`
63			`if opcode='0' then`
64			`if AdressOut = currentstate then`
65			`next_instructie<='0';`
66			`ADR_O<=adress;`
67			`CYC_O<='1';`
68			`WE_O <='0';`
69			`STB_O<='1';`
70			`currentstate<=readwrite;`
71			`timeout<=0;`
72			`elsif currentstate=readwrite then`
73			`if ACK_I='1' then`
74			`CYC_O<='0';`
75			`WE_O <='0';`
76			`STB_O<='0';`
77			`ADR_O<="00000000";`
78			`currentstate<=toqueue;`
79			`db_out<=DAT_I;`
80			`rs232_we<='1';`
81			`timeout<=0;`
82			`elsif timeout=7 then`
83			`CYC_O<='0';`
84			`WE_O <='0';`
85			`STB_O<='0';`
86			`ADR_O<="00000000";`
87			`next_instructie<='1';`
88			`currentstate<=AdressOut;`
89			`error<='1';`
90			`timeout<=0;`
91			`else`
92			`timeout<=timeout+1;`
93			`end if;`
94
95			`elsif currentstate=toqueue then`
96			`if queue_ack='1' then`
97			`rs232_we<='0';`
98			`next_instructie<='1';`
99			`currentstate<=AdressOut;`
100			`enable_int<='0';`
101			`end if;`
102			`end if;`
103
104
105			`--------------------------------write`
106			`else`
107			`if AdressOut =currentstate then`
108			`next_instructie<='0';`
109			`ADR_O<=adress;`
110			`DAT_O<=db_in;`
111			`CYC_O<='1';`
112			`WE_O <='1';`
113			`STB_O<='1';`
114			`currentstate<=readwrite;`
115			`timeout<=0;`
116			`elsif currentstate=readwrite then`
117			`if ACK_I='1' then`
118			`CYC_O<='0';`
119			`WE_O <='0';`
120			`STB_O<='0';`
121			`currentstate<=AdressOut;`
122			`ADR_O<="00000000";`
123			`next_instructie<='1';`
124			`timeout<=0;`
125			`enable_int<='0';`
126			`elsif timeout=7 then`
127			`CYC_O<='0';`
128			`WE_O <='0';`
129			`STB_O<='0';`
130			`ADR_O<="00000000";`
131			`currentstate<=AdressOut;`
132			`error<='1';`
133			`timeout<=0;`
134			`enable_int<='0';`
135			`next_instructie<='1';`
136			`else`
137			`timeout<=timeout+1;`
138			`end if ;`
139			`end if;`
140			`end if;`
141			`end if;`
142			`end if;`
143			`end if;`
144			`end process;`
145			`end Behavioral;`
146

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Subversion Repositories wishbone_uart_controller

[/] [wishbone_uart_controller/] [branches/] [uartcontroller/] [IOALU.vhd] - Blame information for rev 3