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barryw |
--Latest version of all project files available at http://opencores.org/project,wrimm
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--See License.txt for license details
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--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
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--See wrimm subversion project for version history
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library wrimm;
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use wrimm.WrimmPackage.all;
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entity Wb2MasterIntercon is
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generic (
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MasterCount : integer := 1;
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StatusParams : StatusFieldDefType;
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SettingParams : SettingFieldDefType;
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TriggerParams : TriggerFieldDefType);
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port (
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WbClk : in std_logic;
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WbRst : out std_logic;
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WbMasterIn : in WbMasterOutArray(0 to MasterCount-1); --Signals from Masters
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WbMasterOut : out WbSlaveOutArray(0 to MasterCount-1); --Signals to Masters
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WbSlaveIn : out WbMasterOutArray(0 to SlaveCount-1);
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WbSlaveOut : in WbSlaveOutArray(0 to SlaveCount-1)
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StatusRegs : in StatusArrayType;
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SettingRegs : out SettingArrayType;
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SettingRsts : in SettingArrayBitType;
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Triggers : out TriggerArrayType;
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TriggerClr : in TriggerArrayType;
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rstZ : in std_logic); --Asynchronous reset
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end entity Wb2MasterIntercon;
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architecture behavior of Wb2MasterIntercon is
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signal wbStrobe : std_logic;
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signal validAddress : std_logic;
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signal wbAddr : WbAddrType;
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signal wbSData,wbMData : WbDataType;
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signal wbWrEn,wbCyc : std_logic;
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signal wbAck,wbRty,wbErr : std_logic;
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signal wbMDataTag : std_logic_vector(0 to 1);
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signal wbCycType : std_logic_vector(0 to 2);
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signal iSettingRegs : SettingArrayType;
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signal iTriggers : TriggerArrayType;
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signal statusEnable : StatusArrayBitType;
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signal settingEnable : SettingArrayBitType;
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signal triggerEnable : TriggerArrayType;
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signal testEnable,testClr : std_logic;
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signal testNibble : std_logic_vector(0 to 3);
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signal grant : std_logic_vector(0 to MasterCount-1);
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begin
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SettingRegs <= iSettingRegs;
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Triggers <= iTriggers;
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--=============================================================================
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-------------------------------------------------------------------------------
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-- Master Round Robin Arbitration
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-------------------------------------------------------------------------------
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procArb: process(WbClk,rstZ) is --Round robin arbitration (descending)
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variable vGrant : std_logic_vector(0 to MasterCount-1);
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begin
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if (rstZ='0') then
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grant(0) <= '1';
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grant(1 to MasterCount-1) <= (Others=>'0');
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elsif rising_edge(WbClk) then
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loopGrant: for i in 0 to (MasterCount-1) loop
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if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
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loopNewGrantA: for j in i to (MasterCount-1) loop --last master with cyc=1 will be selected
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if WbMasterIn(j).Cyc='1' then
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vGrant := (Others=>'0');
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vGrant(j) := '1';
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end if;
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end loop loopNewGrantA;
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if i/=0 then
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loopNewGrantB: for j in 0 to (i-1) loop
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if WbMasterIn(j).Cyc='0' then
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vGrant := (Others=>'1');
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vGrant(j) := '1';
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end if;
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end loop loopNewGrantB; --grant only moves after new requester
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end if;
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end if;
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end loop loopGrant;
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grant <= vGrant;
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end if; --Clk
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end process procArb;
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--=============================================================================
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-------------------------------------------------------------------------------
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-- Master Mux
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-------------------------------------------------------------------------------
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procWbIn: process(grant,WbMasterIn,wbSData,wbAck,wbErr,wbRty) is
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variable grantId : integer;
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begin
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loopGrantMux: for i in 0 to (MasterCount-1) loop
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--if grant(i)='1' then
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-- grantId := i;
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--end if;
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grantID <= grantID + ((2**i)*to_integer(unsigned(grant(i)),1));
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WbMasterOut(i).Ack <= grant(i) and wbAck;
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WbMasterOut(i).Err <= grant(i) and wbErr;
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WbMasterOut(i).Rty <= grant(i) and wbRty;
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WbMasterOut(i).Data <= wbSData; --Data out can always be active.
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end loop loopGrantMux;
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wbStrobe <= WbMasterIn(grantId).Strobe;
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wbWrEn <= WbMasterIn(grantId).WrEn;
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wbAddr <= WbMasterIn(grantId).Addr;
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wbMData <= WbMasterIn(grantId).Data;
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wbMDataTag <= WbMasterIn(grantId).DataTag;
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wbCyc <= WbMasterIn(grantId).Cyc;
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wbCycType <= WbMasterIn(grantId).CycType;
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end process procWbIn;
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wbAck <= wbStrobe and validAddress;
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wbErr <= wbStrobe and not(validAddress);
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wbRty <= '0';
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WbRst <= '0';
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--=============================================================================
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-------------------------------------------------------------------------------
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-- Address Decode, Asynchronous
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-------------------------------------------------------------------------------
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procAddrDecode: process(wbAddr) is
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variable vValidAddress : std_logic;
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begin
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vValidAddress := '0';
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loopStatusEn: for f in StatusFieldType loop
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if StatusParams(f).Address=wbAddr then
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statusEnable(f) <= '1';
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vValidAddress := '1';
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else
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statusEnable(f) <= '0';
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end if;
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end loop loopStatusEn;
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loopSettingEn: for f in SettingFieldType loop
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if SettingParams(f).Address=wbAddr then
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settingEnable(f) <= '1';
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vValidAddress := '1';
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else
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settingEnable(f) <= '0';
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end if;
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end loop loopSettingEn;
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loopTriggerEn: for f in TriggerFieldType loop
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if TriggerParams(f).Address=wbAddr then
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triggerEnable(f) <= '1';
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vValidAddress := '1';
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else
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triggerEnable(f) <= '0';
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end if;
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end loop loopTriggerEn;
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validAddress <= vValidAddress;
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end process procAddrDecode;
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--=============================================================================
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-------------------------------------------------------------------------------
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-- Read
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-------------------------------------------------------------------------------
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procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is
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variable vWbSData : std_logic_vector(0 to 31);
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begin
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vWbSData := (Others=>'0');
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loopStatusRegs : for f in StatusFieldType loop
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if statusEnable(f)='1' then
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vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1);
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end if; --Address
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end loop loopStatusRegs;
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loopSettingRegs : for f in SettingFieldType loop
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if settingEnable(f)='1' then
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vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1);
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end if; --Address
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end loop loopSettingRegs;
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loopTriggerRegs : for f in TriggerFieldType loop
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if triggerEnable(f)='1' then
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vWbSData(TriggerParams(f).BitLoc) := iTriggers(f);
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end if; --Address
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end loop loopTriggerRegs;
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wbSData <= vWbSData;
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end process procRegRead;
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--=============================================================================
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-------------------------------------------------------------------------------
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-- Write
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-------------------------------------------------------------------------------
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procRegWrite: process(WbClk,rstZ) is
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begin
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if (rstZ='0') then
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loopSettingRegDefault : for f in SettingFieldType loop
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iSettingRegs(f) <= SettingParams(f).Default;
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end loop loopSettingRegDefault;
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loopTriggerRegDefault : for f in TriggerFieldType loop
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iTriggers(f) <= '0';
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end loop loopTriggerRegDefault;
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elsif rising_edge(WbClk) then
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loopSettingRegWr : for f in SettingFieldType loop
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if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
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iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1));
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end if;
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end loop loopSettingRegWr;
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loopSettingRegRst : for f in SettingFieldType loop
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if SettingRsts(f)='1' then
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iSettingRegs(f) <= SettingParams(f).Default;
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end if;
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end loop loopSettingRegRst;
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loopTriggerRegWr : for f in TriggerFieldType loop
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if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
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iTriggers(f) <= wbMData(TriggerParams(f).BitLoc);
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elsif TriggerClr(f)='1' then
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iTriggers(f) <= '0';
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end if; --Address or clear
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end loop loopTriggerRegWr;
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end if; --Clk
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end process procRegWrite;
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testEnable <= settingEnable(SetIntegrationQStop);
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testClr <= settingRsts(SetIntegrationQStop);
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testNibble <= iSettingRegs(SetIntegrationQStop)(28 to 31);
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end architecture behavior;
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