URL https://opencores.org/ocsvn/xilinx_virtex_fp_library/xilinx_virtex_fp_library/trunk

Subversion Repositories xilinx_virtex_fp_library

[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [hp_maf_5_graphics.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:33:40 03/24/2013 
-- Design Name: 
-- Module Name:    hp_maf_5_graphics - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity hp_maf_5_graphics is
                port (clk, rst : in std_logic;
                        mantissa_a, mantissa_b : in std_logic_vector(10 downto 0);
                        mantissa_c : in std_logic_vector (10 downto 0);
                        exp_a, exp_b : in std_logic_vector(4 downto 0);
                        exp_c : in std_logic_vector(4 downto 0);
                        sign_a, sign_b : in std_logic;
                        sign_c : in std_logic;
                        sub : in std_logic;
                        mantissa_res : out std_logic_vector(10 downto 0);
                        exp_res : out std_logic_vector(4 downto 0);
                        sign_res : out std_logic);
end hp_maf_5_graphics;
 
architecture Behavioral of hp_maf_5_graphics is
 
        component exp_add_lzc
                generic( SIZE_EXP : natural := 5;
                                SIZE_LZC : natural := 4);
                port (exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
                                lzc : in std_logic_vector(SIZE_LZC - 1 downto 0);
                                exp_out : out std_logic_vector (SIZE_EXP - 1 downto 0));
        end component;
 
        component exp_add_norm
                generic (SIZE_EXP : natural := 5;
                                PIPELINE : natural := 0);
                port (clk, rst : in std_logic;
                        exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
                        ovf_norm : in std_logic_vector (1 downto 0);
                        ovf_rnd : in std_logic;
                        exp_out : out std_logic_vector(SIZE_EXP - 1 downto 0));
        end component;
 
        component sign_comp
                port (sign_a, sign_b : in std_logic;
                        sign_c : in std_logic;
                        comp_exp : in std_logic;
                        eff_sub : in std_logic;
                        sign_add : in std_logic;
                        sign_res : out std_logic);
        end component;
 
        component exponent_align
                generic (SIZE_EXP : natural := 5;
                                        PIPELINE : natural := 2); -- nr of pipeline registers -- max 2
                port (clk, rst : in std_logic;
                                exp_a, exp_b : in std_logic_vector (SIZE_EXP - 1 downto 0);
                                exp_c : in std_logic_vector (SIZE_EXP - 1 downto 0);
                                align : out std_logic_vector (SIZE_EXP - 1 downto 0);
                                exp_int : out std_logic_vector (SIZE_EXP downto 0);
                                comp : out std_logic);
        end component;
 
        component effective_op is
                port (sign_a, sign_b, sign_c : in std_logic;
                        sub: in std_logic;
                        eff_sub : out std_logic);
        end component;
 
        component shift
                generic (INPUT_SIZE : natural := 13;
                                SHIFT_SIZE : natural := 4;
                                OUTPUT_SIZE : natural := 24;
                                DIRECTION : natural := 1;  -- 1 for left shift; 0 for right shift
                                PIPELINE : natural := 1;
                                POSITION : std_logic_vector(7 downto 0) := "00000000"); -- number of pipeline registers
                port (clk, rst : in std_logic;
                        a : in std_logic_vector (INPUT_SIZE - 1 downto 0);
                        arith : in std_logic;
                        shft : in std_logic_vector (SHIFT_SIZE - 1 downto 0);
                        shifted_a : out std_logic_vector (OUTPUT_SIZE - 1 downto 0));
        end component;
 
        component round_norm
                generic ( OPERAND_SIZE : natural := 24;
                                MANTISSA_SIZE : natural := 12;
                                RND_PREC : natural := 0; --0 RNE, 1 Trunc
                                PIPELINE: natural := 1); -- 0 - no pipeline
                port ( clk, rst : std_logic;
                        mantissa_in : in std_logic_vector (OPERAND_SIZE + 1 downto 0);
                        mantissa_out: out std_logic_vector (MANTISSA_SIZE - 1 downto 0);
                        neg : in std_logic;
                        ovf_norm : out std_logic_vector(1 downto 0);
                        ovf_rnd : out std_logic);
        end component;
 
        component dsp_unit
                generic (MULT_REG : natural := 1;
                        MULT_STRING : string := "MULT_S");
                port (clk, rst : in std_logic;
                        a : in std_logic_vector(23 downto 0);
                        b : in std_logic_vector (16 downto 0);
                        c : in std_logic_vector (32 downto 0);
                        comp : in std_logic; -- 1 for a*b > c ; 0 for a*b <c
                        sub : in std_logic;
                        acc : in std_logic; -- 0 for add; 1 for accumulate
                        p: out std_logic_vector (35 downto 0);
                        pattern_detect : out std_logic;
                        ovf, udf : out std_logic);
        end component;
 
        component d_ff
                generic (N: natural := 8);
                port (clk, rst : in std_logic;
                                d : in std_logic_vector (N-1 downto 0);
                                q : out std_logic_vector (N-1 downto 0));
        end component;
 
        component lzc_tree
                generic (SIZE_INT : natural := 42;
                                PIPELINE : natural := 2);
                port (clk, rst : in std_logic;
                        a  : in std_logic_vector(SIZE_INT - 1 downto 0);
                        ovf : in std_logic;
                        lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));
        end component;
 
        signal mantissa_a_q : std_logic_vector(10 downto 0) := (others => '0');
   signal mantissa_b_q : std_logic_vector(10 downto 0) := (others => '0');
   signal mantissa_c_q : std_logic_vector(10 downto 0) := (others => '0');
--   signal sign_a_q : std_logic := '0';
--   signal sign_b_q : std_logic := '0';
--   signal sign_c_q : std_logic := '0';
   signal sub_q : std_logic := '0';
 
 
        signal eff_sub : std_logic;
        signal comp : std_logic;
        signal align : std_logic_vector (4 downto 0);
        signal align_q : std_logic_vector (4 downto 0);
        signal exp_int : std_logic_vector (5 downto 0);
        signal exp_int_q0 : std_logic_vector (5 downto 0);
        signal exp_int_q1 : std_logic_vector (5 downto 0);
        signal exp_int_q2 : std_logic_vector (5 downto 0);
        signal exp_int_q3 : std_logic_vector (5 downto 0);
        signal exp_int_q4 : std_logic_vector (5 downto 0);
        signal exp_int_q5 : std_logic_vector (5 downto 0);
        signal exp_lzc_d, exp_lzc_q : std_logic_vector (5 downto 0);
        signal exp_res_int : std_logic_vector (5 downto 0);
 
        signal align_a : std_logic_vector(4 downto 0);
        signal align_c : std_logic_vector(4 downto 0);
 
        signal aligned_mantissa_a : std_logic_vector(22 downto 0);
        signal a_input: std_logic_vector(23 downto 0);
        signal aligned_mantissa_c_d : std_logic_vector(32 downto 0);
        signal aligned_mantissa_c_q : std_logic_vector(32 downto 0);
        signal b_input : std_logic_vector (16 downto 0);
 
 
        signal sub_vec0, comp_vec0 : std_logic_vector(0 downto 0);
        signal sub_dsp, comp_dsp : std_logic_vector(0 downto 0);
        signal sub_vec, comp_vec : std_logic_vector(0 downto 0);
        signal sub_dsp1, comp_dsp1 : std_logic_vector(0 downto 0);
        signal sub_dsp2, comp_dsp2 : std_logic_vector(0 downto 0);
        signal sign_d: std_logic_vector (2 downto 0);
        signal sign_q0, sign_q1 : std_logic_vector (2 downto 0);
        signal sign_q2, sign_q3 : std_logic_vector (2 downto 0);
        signal acc : std_logic;
 
        signal mantissa_mac : std_logic_vector (35 downto 0);
        signal mantissa_abs_d, mantissa_abs_q: std_logic_vector (23 downto 0);
        signal mantissa_abs_q1 : std_logic_vector (23 downto 0);
        signal mantissa_lzc_d : std_logic_vector (23 downto 0);
        signal mantissa_lzc_q : std_logic_vector (23 downto 0);
        signal lzc_d, lzc_q : std_logic_vector (4 downto 0);
        signal mantissa_res_d: std_logic_vector (10 downto 0);
 
        signal sign_res1, sign_res2, sign_res3, sign_res4, sign_res5 : std_logic_vector(0 downto 0);
 
        signal ovf_round: std_logic;
        signal ovf_norm : std_logic_vector (1 downto 0);
        signal sign_mantissa_add : std_logic;
        signal ovf_mac : std_logic;
 
        signal neg1, neg2, neg3, neg4 : std_logic_vector(0 downto 0);
 
        signal res_zero1, res_zero2, res_zero3, res_zero4, res_zero5 : std_logic_vector(0 downto 0);
 
        signal zero : std_logic;
 
begin
 
                zero <= '0';
 
        --STAGE 1
 
 
 
        EFFECTIVE_SUB:
                effective_op port map (sign_a => sign_a, sign_b => sign_b,
                                                                sign_c => sign_c,
                                                                sub => sub, eff_sub => eff_sub);
 
        EXP_ALIGN : exponent_align
                                                generic map (SIZE_EXP => 5, PIPELINE => 0)
                                                port map (clk => clk, rst => rst,
                                                        exp_a => exp_a, exp_b => exp_b,
                                                        exp_c => exp_c, align => align,
                                                        exp_int => exp_int, comp=>comp);
 
        acc <= '0';
 
        sub_vec0(0) <= eff_sub;
        comp_vec0(0) <= comp;
 
        sign_d(0) <= sign_c;
        sign_d(1) <= sign_b;
        sign_d(2) <= sign_a;
 
        --pipeline stage 0
--      LATCH_A_S0: d_ff
--                                      generic map ( N => 11)
--                                      port map (clk => clk, rst => rst, 
--                                                      d => mantissa_a, q => mantissa_a_q);
--      
        LATCH_B_S0: d_ff
                                        generic map ( N => 11)
                                        port map (clk => clk, rst => rst,
                                                        d => mantissa_b, q => mantissa_b_q);
--      
--      LATCH_C_S0: d_ff
--                                      generic map ( N => 11)
--                                      port map (clk => clk, rst => rst, 
--                                                      d => mantissa_c, q => mantissa_c_q);
 
 
        LATCH_sub_S0: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_vec0, q => sub_vec);
 
        LATCH_comp_S0: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_vec0, q => comp_vec);
 
        LATCH_sign_S0 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_d, q => sign_q0);
 
        LATCH_exp_S0 : d_ff
                                        generic map (N => 6)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int, q => exp_int_q0);
 
        LATCH_ALIGN: d_ff
                                        generic map (N=>5)
                                        port map (clk => clk, rst => rst,
                                                                d=> align, q => align_q);
 
 
        align_a(4 downto 1) <= align_q(4 downto 1) when comp_vec(0) = '0' else
                                                                        (others => '0');
 
        align_a(0 downto 0) <= align(0 downto 0) when comp_vec0(0) = '0' else
                                                                        (others => '0');
 
        align_c(4 downto 1) <= align_q(4 downto 1) when comp_vec(0) = '1' else
                                                                        (others => '0');
 
        align_c(0 downto 0) <= align(0 downto 0) when comp_vec0(0) = '1' else
                                                                        (others => '0');
 
--      align_a <= align_q(4 downto 0)  when comp_vec(0) = '0' else 
--                              (others => '0');
--      
--      align_c <= align_q when comp_vec(0) = '1' else
--                                      (others => '0');
 
        SHIFT_A : shift
                                        generic map (INPUT_SIZE => 11,
                                                                        SHIFT_SIZE => 5,
                                                                        OUTPUT_SIZE => 23,
                                                                        DIRECTION => 0,
                                                                        PIPELINE => 1,
                                                                        POSITION => "00000001")
                                        port map (clk => clk, rst => rst,
                                                        a => mantissa_a,
                                                        arith => zero,
                                                        shft => align_a,
                                                        shifted_a => aligned_mantissa_a);
 
        SHIFT_C : shift
                                        generic map (INPUT_SIZE => 11,
                                                                        SHIFT_SIZE => 5,
                                                                        OUTPUT_SIZE => 33,
                                                                        DIRECTION => 0,
                                                                        PIPELINE => 1,
                                                                        POSITION => "00000001")
                                        port map (clk => clk, rst => rst,
                                                        a => mantissa_c,
                                                        arith => zero,
                                                        shft => align_c,
                                                        shifted_a => aligned_mantissa_c_d);
 
        b_input <=(16 downto 11 => '0')& mantissa_b_q;
        a_input <= "0" & aligned_mantissa_a;
-- first pipeline register 
-- latching mantissa_c, sub_eff, comp, exp_int, signs 
-- a and b are latched inside the dsp block     
 
        aligned_mantissa_c_q <= aligned_mantissa_c_d;
        sub_dsp <= sub_vec;
        comp_dsp <= comp_vec;
        sign_q1 <= sign_q0;
        exp_int_q1 <= exp_int_q0;
 
 
-- instantiating dsp
 
        DSP: dsp_unit
                                generic map(0, "MULT")
                                port map(clk => clk, rst => rst,
                                                a => a_input,
                                                b => b_input,
                                                c => aligned_mantissa_c_q,
                                                comp => comp_dsp(0), -- 1 for a*b > c ; 0 for a*b <c
                                                sub => sub_dsp(0),
                                                acc => acc, -- 0 for add; 1 for accumulate
                                                p => mantissa_mac,
                                                pattern_detect => res_zero1(0),
                                                ovf => open, udf => open);
 
 
        --2 pipeline registers for other signals
        -- exp_int, signs, eff_sub 
 
 
 
        LATCH_sub_S2: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_dsp, q => sub_dsp1);
 
        LATCH_comp_S2: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_dsp, q => comp_dsp1);
 
        LATCH_sign_S2 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q1, q => sign_q2);
 
        LATCH_exp_S2 : d_ff
                                        generic map (N => 6)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q1, q => exp_int_q2);
 
        LATCH_sub_S3: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_dsp1, q => sub_dsp2);
 
        LATCH_comp_S3: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_dsp1, q => comp_dsp2);
 
        LATCH_sign_S3 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q2, q => sign_q3);
 
        LATCH_exp_S3 : d_ff
                                        generic map (N => 6)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q2, q => exp_int_q3);
 
        --absolute value 
        sign_mantissa_add <= mantissa_mac(35);
        neg1(0) <= sign_mantissa_add;
 
        mantissa_abs_d <= mantissa_mac (34 downto 11) when sign_mantissa_add = '0' else
                                                        not(mantissa_mac(34 downto 11));
 
        SIGN_RESULT_COMP :
                        sign_comp
                                port map(sign_a => sign_q3(2), sign_b => sign_q3(1),
                                        sign_c => sign_q3(0),
                                        comp_exp => comp_dsp2(0),
                                        eff_sub => sub_dsp2(0),
                                        sign_add => sign_mantissa_add,
                                        sign_res => sign_res1(0));
 
        -- FOURTH PIPELINE REGISTERS
        -- abs value of mantissa, exp_int, sign_res
        mantissa_abs_q <= mantissa_abs_d;
        sign_res2 <= sign_res1;
        exp_int_q4 <= exp_int_q3;
        res_zero2 <= res_zero1;
        neg2 <= neg1;
 
 
 
        --pipeline stage
        ovf_mac <= mantissa_abs_q(23) or mantissa_abs_q(22);
 
        LZC_COUNT : lzc_tree
                                        generic map ( SIZE_INT => 22,
                                                                                PIPELINE => 0)
                                        port map (clk => clk, rst => rst,
                                                                a => mantissa_abs_q(21 downto 0),
                                                                ovf => ovf_mac, lz => lzc_d);
 
        --pipeline register
        LATCH_MANTISSA_ABS_S5:
                d_ff generic map (n => 24)
                                port map (clk => clk, rst => rst,
                                                        d => mantissa_abs_q, q=>mantissa_abs_q1);
 
        LATCH_sign_res_S5 : d_ff
                                        generic map (N => 1)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_res2, q => sign_res3);
 
        LATCH_exp_S5 : d_ff
                                        generic map (N => 6)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q4, q => exp_int_q5);
 
        LATCH_lzc_S5 : d_ff
                                        generic map (N => 5)
                                        port map (clk => clk, rst => rst,
                                                                d=> lzc_d, q => lzc_q);
 
        LATCH_ZERO_S5: d_ff
                                        generic map(N=>1)
                                        port map(clk => clk, rst =>rst,
                                                                d=>res_zero2, q=>res_zero3);
 
        LATCH_NEG_S5: d_ff
                                        generic map(N=>1)
                                        port map(clk => clk, rst =>rst,
                                                                d=>neg2, q=>neg3);
 
 
 
        SHIFT_MANTISSA : shift
                                                generic map (INPUT_SIZE => 24,
                                                                                SHIFT_SIZE => 5,
                                                                                OUTPUT_SIZE => 24,
                                                                                DIRECTION => 1,
                                                                                PIPELINE => 0)
                                                port map (clk => clk, rst => rst,
                                                                a => mantissa_abs_q1,
                                                                arith => neg3(0),
                                                                shft => lzc_q,
                                                                shifted_a => mantissa_lzc_d);
 
        SUB_LZC_EXP :
                exp_add_lzc
                        generic map(SIZE_EXP => 6, SIZE_LZC => 5)
                        port map (exp_in => exp_int_q5, lzc => lzc_q, exp_out => exp_lzc_d);
 
        -- pipeline register 6
        -- mantissa_lzc, exp_lzc, sign_res
--      LATCH_MANTISSA_LZC_S6:
--                              d_ff generic map (n => 24)
--                                              port map (clk => clk, rst => rst,
--                                                                      d => mantissa_lzc_d, q=>mantissa_lzc_q);
 
        mantissa_lzc_q <= mantissa_lzc_d;
        sign_res4 <= sign_res3;
        exp_lzc_q <= exp_lzc_d;
        res_zero4 <= res_zero3;
        neg4 <= neg3;
 
--      
--      LATCH_sign_res_S6 : d_ff
--                                      generic map (N => 1)
--                                      port map (clk => clk, rst => rst,
--                                                              d=> sign_res3, q => sign_res4);
--      
--      LATCH_exp_S6 : d_ff 
--                                      generic map (N => 6)
--                                      port map (clk => clk, rst => rst,
--                                                              d=> exp_lzc_d, q => exp_lzc_q);
--                                                              
--      LATCH_ZERO_S6: d_ff 
--                                      generic map(N=>1)
--                                      port map(clk => clk, rst =>rst,
--                                                              d=>res_zero3, q=>res_zero4);
 
--      LATCH_NEG_S6: d_ff 
--                                      generic map(N=>1)
--                                      port map(clk => clk, rst =>rst,
--                                                              d=>neg3, q=>neg4);
 
        --rounding
        ROUND:
                round_norm generic map(OPERAND_SIZE => 22,
                                                                                MANTISSA_SIZE => 11,
                                                                                RND_PREC => 1,
                                                                                PIPELINE => 0)
                                                port map (clk => clk, rst => rst,
                                                                        mantissa_in => mantissa_lzc_q,
                                                                        mantissa_out => mantissa_res_d,
                                                                        neg => neg4(0),
                                                                        ovf_norm => ovf_norm,
                                                                        ovf_rnd => ovf_round);
 
        EXP_UPDATE:
                exp_add_norm generic map (SIZE_EXP => 6, PIPELINE => 0)
                                                port map (clk => clk, rst => rst,
                                                        exp_in => exp_lzc_q,
                                                        ovf_norm => ovf_norm,
                                                        ovf_rnd => ovf_round,
                                                        exp_out => exp_res_int);
 
        --PIPELINE_STAGE 6
        -- sign res
 
--              sign_res5 <= sign_res4;
                sign_res5 <= sign_res4;
                res_zero5 <= res_zero4;
 
                sign_res <= sign_res5(0);
                exp_res <= exp_res_int (4 downto 0) when res_zero5(0) = '0' else
                                        (others =>'0');
                mantissa_res <= mantissa_res_d when res_zero5(0) = '0' else
                                        (others => '0');
 
 
end Behavioral;
 

Browse

Tools

Subversion Repositories xilinx_virtex_fp_library

[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [hp_maf_5_graphics.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	bigsascha3	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 15:33:40 03/24/2013`
6			`-- Design Name:`
7			`-- Module Name: hp_maf_5_graphics - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.std_logic_signed.all;`
23			`use IEEE.std_logic_arith.all;`
24			`use IEEE.math_real.all;`
25
26			`-- Uncomment the following library declaration if using`
27			`-- arithmetic functions with Signed or Unsigned values`
28			`--use IEEE.NUMERIC_STD.ALL;`
29
30			`-- Uncomment the following library declaration if instantiating`
31			`-- any Xilinx primitives in this code.`
32			`--library UNISIM;`
33			`--use UNISIM.VComponents.all;`
34
35			`entity hp_maf_5_graphics is`
36			`port (clk, rst : in std_logic;`
37			`mantissa_a, mantissa_b : in std_logic_vector(10 downto 0);`
38			`mantissa_c : in std_logic_vector (10 downto 0);`
39			`exp_a, exp_b : in std_logic_vector(4 downto 0);`
40			`exp_c : in std_logic_vector(4 downto 0);`
41			`sign_a, sign_b : in std_logic;`
42			`sign_c : in std_logic;`
43			`sub : in std_logic;`
44			`mantissa_res : out std_logic_vector(10 downto 0);`
45			`exp_res : out std_logic_vector(4 downto 0);`
46			`sign_res : out std_logic);`
47			`end hp_maf_5_graphics;`
48
49			`architecture Behavioral of hp_maf_5_graphics is`
50
51			`component exp_add_lzc`
52			`generic( SIZE_EXP : natural := 5;`
53			`SIZE_LZC : natural := 4);`
54			`port (exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);`
55			`lzc : in std_logic_vector(SIZE_LZC - 1 downto 0);`
56			`exp_out : out std_logic_vector (SIZE_EXP - 1 downto 0));`
57			`end component;`
58
59			`component exp_add_norm`
60			`generic (SIZE_EXP : natural := 5;`
61			`PIPELINE : natural := 0);`
62			`port (clk, rst : in std_logic;`
63			`exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);`
64			`ovf_norm : in std_logic_vector (1 downto 0);`
65			`ovf_rnd : in std_logic;`
66			`exp_out : out std_logic_vector(SIZE_EXP - 1 downto 0));`
67			`end component;`
68
69			`component sign_comp`
70			`port (sign_a, sign_b : in std_logic;`
71			`sign_c : in std_logic;`
72			`comp_exp : in std_logic;`
73			`eff_sub : in std_logic;`
74			`sign_add : in std_logic;`
75			`sign_res : out std_logic);`
76			`end component;`
77
78			`component exponent_align`
79			`generic (SIZE_EXP : natural := 5;`
80			`PIPELINE : natural := 2); -- nr of pipeline registers -- max 2`
81			`port (clk, rst : in std_logic;`
82			`exp_a, exp_b : in std_logic_vector (SIZE_EXP - 1 downto 0);`
83			`exp_c : in std_logic_vector (SIZE_EXP - 1 downto 0);`
84			`align : out std_logic_vector (SIZE_EXP - 1 downto 0);`
85			`exp_int : out std_logic_vector (SIZE_EXP downto 0);`
86			`comp : out std_logic);`
87			`end component;`
88
89			`component effective_op is`
90			`port (sign_a, sign_b, sign_c : in std_logic;`
91			`sub: in std_logic;`
92			`eff_sub : out std_logic);`
93			`end component;`
94
95			`component shift`
96			`generic (INPUT_SIZE : natural := 13;`
97			`SHIFT_SIZE : natural := 4;`
98			`OUTPUT_SIZE : natural := 24;`
99			`DIRECTION : natural := 1; -- 1 for left shift; 0 for right shift`
100			`PIPELINE : natural := 1;`
101			`POSITION : std_logic_vector(7 downto 0) := "00000000"); -- number of pipeline registers`
102			`port (clk, rst : in std_logic;`
103			`a : in std_logic_vector (INPUT_SIZE - 1 downto 0);`
104			`arith : in std_logic;`
105			`shft : in std_logic_vector (SHIFT_SIZE - 1 downto 0);`
106			`shifted_a : out std_logic_vector (OUTPUT_SIZE - 1 downto 0));`
107			`end component;`
108
109			`component round_norm`
110			`generic ( OPERAND_SIZE : natural := 24;`
111			`MANTISSA_SIZE : natural := 12;`
112			`RND_PREC : natural := 0; --0 RNE, 1 Trunc`
113			`PIPELINE: natural := 1); -- 0 - no pipeline`
114			`port ( clk, rst : std_logic;`
115			`mantissa_in : in std_logic_vector (OPERAND_SIZE + 1 downto 0);`
116			`mantissa_out: out std_logic_vector (MANTISSA_SIZE - 1 downto 0);`
117			`neg : in std_logic;`
118			`ovf_norm : out std_logic_vector(1 downto 0);`
119			`ovf_rnd : out std_logic);`
120			`end component;`
121
122			`component dsp_unit`
123			`generic (MULT_REG : natural := 1;`
124			`MULT_STRING : string := "MULT_S");`
125			`port (clk, rst : in std_logic;`
126			`a : in std_logic_vector(23 downto 0);`
127			`b : in std_logic_vector (16 downto 0);`
128			`c : in std_logic_vector (32 downto 0);`
129			`comp : in std_logic; -- 1 for ab > c ; 0 for ab <c`
130			`sub : in std_logic;`
131			`acc : in std_logic; -- 0 for add; 1 for accumulate`
132			`p: out std_logic_vector (35 downto 0);`
133			`pattern_detect : out std_logic;`
134			`ovf, udf : out std_logic);`
135			`end component;`
136
137			`component d_ff`
138			`generic (N: natural := 8);`
139			`port (clk, rst : in std_logic;`
140			`d : in std_logic_vector (N-1 downto 0);`
141			`q : out std_logic_vector (N-1 downto 0));`
142			`end component;`
143
144			`component lzc_tree`
145			`generic (SIZE_INT : natural := 42;`
146			`PIPELINE : natural := 2);`
147			`port (clk, rst : in std_logic;`
148			`a : in std_logic_vector(SIZE_INT - 1 downto 0);`
149			`ovf : in std_logic;`
150			`lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));`
151			`end component;`
152
153			`signal mantissa_a_q : std_logic_vector(10 downto 0) := (others => '0');`
154			`signal mantissa_b_q : std_logic_vector(10 downto 0) := (others => '0');`
155			`signal mantissa_c_q : std_logic_vector(10 downto 0) := (others => '0');`
156			`-- signal sign_a_q : std_logic := '0';`
157			`-- signal sign_b_q : std_logic := '0';`
158			`-- signal sign_c_q : std_logic := '0';`
159			`signal sub_q : std_logic := '0';`
160
161
162			`signal eff_sub : std_logic;`
163			`signal comp : std_logic;`
164			`signal align : std_logic_vector (4 downto 0);`
165			`signal align_q : std_logic_vector (4 downto 0);`
166			`signal exp_int : std_logic_vector (5 downto 0);`
167			`signal exp_int_q0 : std_logic_vector (5 downto 0);`
168			`signal exp_int_q1 : std_logic_vector (5 downto 0);`
169			`signal exp_int_q2 : std_logic_vector (5 downto 0);`
170			`signal exp_int_q3 : std_logic_vector (5 downto 0);`
171			`signal exp_int_q4 : std_logic_vector (5 downto 0);`
172			`signal exp_int_q5 : std_logic_vector (5 downto 0);`
173			`signal exp_lzc_d, exp_lzc_q : std_logic_vector (5 downto 0);`
174			`signal exp_res_int : std_logic_vector (5 downto 0);`
175
176			`signal align_a : std_logic_vector(4 downto 0);`
177			`signal align_c : std_logic_vector(4 downto 0);`
178
179			`signal aligned_mantissa_a : std_logic_vector(22 downto 0);`
180			`signal a_input: std_logic_vector(23 downto 0);`
181			`signal aligned_mantissa_c_d : std_logic_vector(32 downto 0);`
182			`signal aligned_mantissa_c_q : std_logic_vector(32 downto 0);`
183			`signal b_input : std_logic_vector (16 downto 0);`
184
185
186			`signal sub_vec0, comp_vec0 : std_logic_vector(0 downto 0);`
187			`signal sub_dsp, comp_dsp : std_logic_vector(0 downto 0);`
188			`signal sub_vec, comp_vec : std_logic_vector(0 downto 0);`
189			`signal sub_dsp1, comp_dsp1 : std_logic_vector(0 downto 0);`
190			`signal sub_dsp2, comp_dsp2 : std_logic_vector(0 downto 0);`
191			`signal sign_d: std_logic_vector (2 downto 0);`
192			`signal sign_q0, sign_q1 : std_logic_vector (2 downto 0);`
193			`signal sign_q2, sign_q3 : std_logic_vector (2 downto 0);`
194			`signal acc : std_logic;`
195
196			`signal mantissa_mac : std_logic_vector (35 downto 0);`
197			`signal mantissa_abs_d, mantissa_abs_q: std_logic_vector (23 downto 0);`
198			`signal mantissa_abs_q1 : std_logic_vector (23 downto 0);`
199			`signal mantissa_lzc_d : std_logic_vector (23 downto 0);`
200			`signal mantissa_lzc_q : std_logic_vector (23 downto 0);`
201			`signal lzc_d, lzc_q : std_logic_vector (4 downto 0);`
202			`signal mantissa_res_d: std_logic_vector (10 downto 0);`
203
204			`signal sign_res1, sign_res2, sign_res3, sign_res4, sign_res5 : std_logic_vector(0 downto 0);`
205
206			`signal ovf_round: std_logic;`
207			`signal ovf_norm : std_logic_vector (1 downto 0);`
208			`signal sign_mantissa_add : std_logic;`
209			`signal ovf_mac : std_logic;`
210
211			`signal neg1, neg2, neg3, neg4 : std_logic_vector(0 downto 0);`
212
213			`signal res_zero1, res_zero2, res_zero3, res_zero4, res_zero5 : std_logic_vector(0 downto 0);`
214
215			`signal zero : std_logic;`
216
217			`begin`
218
219			`zero <= '0';`
220
221			`--STAGE 1`
222
223
224
225			`EFFECTIVE_SUB:`
226			`effective_op port map (sign_a => sign_a, sign_b => sign_b,`
227			`sign_c => sign_c,`
228			`sub => sub, eff_sub => eff_sub);`
229
230			`EXP_ALIGN : exponent_align`
231			`generic map (SIZE_EXP => 5, PIPELINE => 0)`
232			`port map (clk => clk, rst => rst,`
233			`exp_a => exp_a, exp_b => exp_b,`
234			`exp_c => exp_c, align => align,`
235			`exp_int => exp_int, comp=>comp);`
236
237			`acc <= '0';`
238
239			`sub_vec0(0) <= eff_sub;`
240			`comp_vec0(0) <= comp;`
241
242			`sign_d(0) <= sign_c;`
243			`sign_d(1) <= sign_b;`
244			`sign_d(2) <= sign_a;`
245
246			`--pipeline stage 0`
247			`-- LATCH_A_S0: d_ff`
248			`-- generic map ( N => 11)`
249			`-- port map (clk => clk, rst => rst,`
250			`-- d => mantissa_a, q => mantissa_a_q);`
251			`--`
252			`LATCH_B_S0: d_ff`
253			`generic map ( N => 11)`
254			`port map (clk => clk, rst => rst,`
255			`d => mantissa_b, q => mantissa_b_q);`
256			`--`
257			`-- LATCH_C_S0: d_ff`
258			`-- generic map ( N => 11)`
259			`-- port map (clk => clk, rst => rst,`
260			`-- d => mantissa_c, q => mantissa_c_q);`
261
262
263			`LATCH_sub_S0: d_ff`
264			`generic map ( N => 1)`
265			`port map ( clk => clk, rst => rst,`
266			`d=> sub_vec0, q => sub_vec);`
267
268			`LATCH_comp_S0: d_ff`
269			`generic map ( N => 1)`
270			`port map ( clk => clk, rst => rst,`
271			`d=> comp_vec0, q => comp_vec);`
272
273			`LATCH_sign_S0 : d_ff`
274			`generic map (N => 3)`
275			`port map (clk => clk, rst => rst,`
276			`d=> sign_d, q => sign_q0);`
277
278			`LATCH_exp_S0 : d_ff`
279			`generic map (N => 6)`
280			`port map (clk => clk, rst => rst,`
281			`d=> exp_int, q => exp_int_q0);`
282
283			`LATCH_ALIGN: d_ff`
284			`generic map (N=>5)`
285			`port map (clk => clk, rst => rst,`
286			`d=> align, q => align_q);`
287
288
289			`align_a(4 downto 1) <= align_q(4 downto 1) when comp_vec(0) = '0' else`
290			`(others => '0');`
291
292			`align_a(0 downto 0) <= align(0 downto 0) when comp_vec0(0) = '0' else`
293			`(others => '0');`
294
295			`align_c(4 downto 1) <= align_q(4 downto 1) when comp_vec(0) = '1' else`
296			`(others => '0');`
297
298			`align_c(0 downto 0) <= align(0 downto 0) when comp_vec0(0) = '1' else`
299			`(others => '0');`
300
301			`-- align_a <= align_q(4 downto 0) when comp_vec(0) = '0' else`
302			`-- (others => '0');`
303			`--`
304			`-- align_c <= align_q when comp_vec(0) = '1' else`
305			`-- (others => '0');`
306
307			`SHIFT_A : shift`
308			`generic map (INPUT_SIZE => 11,`
309			`SHIFT_SIZE => 5,`
310			`OUTPUT_SIZE => 23,`
311			`DIRECTION => 0,`
312			`PIPELINE => 1,`
313			`POSITION => "00000001")`
314			`port map (clk => clk, rst => rst,`
315			`a => mantissa_a,`
316			`arith => zero,`
317			`shft => align_a,`
318			`shifted_a => aligned_mantissa_a);`
319
320			`SHIFT_C : shift`
321			`generic map (INPUT_SIZE => 11,`
322			`SHIFT_SIZE => 5,`
323			`OUTPUT_SIZE => 33,`
324			`DIRECTION => 0,`
325			`PIPELINE => 1,`
326			`POSITION => "00000001")`
327			`port map (clk => clk, rst => rst,`
328			`a => mantissa_c,`
329			`arith => zero,`
330			`shft => align_c,`
331			`shifted_a => aligned_mantissa_c_d);`
332
333			`b_input <=(16 downto 11 => '0')& mantissa_b_q;`
334			`a_input <= "0" & aligned_mantissa_a;`
335			`-- first pipeline register`
336			`-- latching mantissa_c, sub_eff, comp, exp_int, signs`
337			`-- a and b are latched inside the dsp block`
338
339			`aligned_mantissa_c_q <= aligned_mantissa_c_d;`
340			`sub_dsp <= sub_vec;`
341			`comp_dsp <= comp_vec;`
342			`sign_q1 <= sign_q0;`
343			`exp_int_q1 <= exp_int_q0;`
344
345
346			`-- instantiating dsp`
347
348			`DSP: dsp_unit`
349			`generic map(0, "MULT")`
350			`port map(clk => clk, rst => rst,`
351			`a => a_input,`
352			`b => b_input,`
353			`c => aligned_mantissa_c_q,`
354			`comp => comp_dsp(0), -- 1 for ab > c ; 0 for ab <c`
355			`sub => sub_dsp(0),`
356			`acc => acc, -- 0 for add; 1 for accumulate`
357			`p => mantissa_mac,`
358			`pattern_detect => res_zero1(0),`
359			`ovf => open, udf => open);`
360
361
362			`--2 pipeline registers for other signals`
363			`-- exp_int, signs, eff_sub`
364
365
366
367			`LATCH_sub_S2: d_ff`
368			`generic map ( N => 1)`
369			`port map ( clk => clk, rst => rst,`
370			`d=> sub_dsp, q => sub_dsp1);`
371
372			`LATCH_comp_S2: d_ff`
373			`generic map ( N => 1)`
374			`port map ( clk => clk, rst => rst,`
375			`d=> comp_dsp, q => comp_dsp1);`
376
377			`LATCH_sign_S2 : d_ff`
378			`generic map (N => 3)`
379			`port map (clk => clk, rst => rst,`
380			`d=> sign_q1, q => sign_q2);`
381
382			`LATCH_exp_S2 : d_ff`
383			`generic map (N => 6)`
384			`port map (clk => clk, rst => rst,`
385			`d=> exp_int_q1, q => exp_int_q2);`
386
387			`LATCH_sub_S3: d_ff`
388			`generic map ( N => 1)`
389			`port map ( clk => clk, rst => rst,`
390			`d=> sub_dsp1, q => sub_dsp2);`
391
392			`LATCH_comp_S3: d_ff`
393			`generic map ( N => 1)`
394			`port map ( clk => clk, rst => rst,`
395			`d=> comp_dsp1, q => comp_dsp2);`
396
397			`LATCH_sign_S3 : d_ff`
398			`generic map (N => 3)`
399			`port map (clk => clk, rst => rst,`
400			`d=> sign_q2, q => sign_q3);`
401
402			`LATCH_exp_S3 : d_ff`
403			`generic map (N => 6)`
404			`port map (clk => clk, rst => rst,`
405			`d=> exp_int_q2, q => exp_int_q3);`
406
407			`--absolute value`
408			`sign_mantissa_add <= mantissa_mac(35);`
409			`neg1(0) <= sign_mantissa_add;`
410
411			`mantissa_abs_d <= mantissa_mac (34 downto 11) when sign_mantissa_add = '0' else`
412			`not(mantissa_mac(34 downto 11));`
413
414			`SIGN_RESULT_COMP :`
415			`sign_comp`
416			`port map(sign_a => sign_q3(2), sign_b => sign_q3(1),`
417			`sign_c => sign_q3(0),`
418			`comp_exp => comp_dsp2(0),`
419			`eff_sub => sub_dsp2(0),`
420			`sign_add => sign_mantissa_add,`
421			`sign_res => sign_res1(0));`
422
423			`-- FOURTH PIPELINE REGISTERS`
424			`-- abs value of mantissa, exp_int, sign_res`
425			`mantissa_abs_q <= mantissa_abs_d;`
426			`sign_res2 <= sign_res1;`
427			`exp_int_q4 <= exp_int_q3;`
428			`res_zero2 <= res_zero1;`
429			`neg2 <= neg1;`
430
431
432
433			`--pipeline stage`
434			`ovf_mac <= mantissa_abs_q(23) or mantissa_abs_q(22);`
435
436			`LZC_COUNT : lzc_tree`
437			`generic map ( SIZE_INT => 22,`
438			`PIPELINE => 0)`
439			`port map (clk => clk, rst => rst,`
440			`a => mantissa_abs_q(21 downto 0),`
441			`ovf => ovf_mac, lz => lzc_d);`
442
443			`--pipeline register`
444			`LATCH_MANTISSA_ABS_S5:`
445			`d_ff generic map (n => 24)`
446			`port map (clk => clk, rst => rst,`
447			`d => mantissa_abs_q, q=>mantissa_abs_q1);`
448
449			`LATCH_sign_res_S5 : d_ff`
450			`generic map (N => 1)`
451			`port map (clk => clk, rst => rst,`
452			`d=> sign_res2, q => sign_res3);`
453
454			`LATCH_exp_S5 : d_ff`
455			`generic map (N => 6)`
456			`port map (clk => clk, rst => rst,`
457			`d=> exp_int_q4, q => exp_int_q5);`
458
459			`LATCH_lzc_S5 : d_ff`
460			`generic map (N => 5)`
461			`port map (clk => clk, rst => rst,`
462			`d=> lzc_d, q => lzc_q);`
463
464			`LATCH_ZERO_S5: d_ff`
465			`generic map(N=>1)`
466			`port map(clk => clk, rst =>rst,`
467			`d=>res_zero2, q=>res_zero3);`
468
469			`LATCH_NEG_S5: d_ff`
470			`generic map(N=>1)`
471			`port map(clk => clk, rst =>rst,`
472			`d=>neg2, q=>neg3);`
473
474
475
476			`SHIFT_MANTISSA : shift`
477			`generic map (INPUT_SIZE => 24,`
478			`SHIFT_SIZE => 5,`
479			`OUTPUT_SIZE => 24,`
480			`DIRECTION => 1,`
481			`PIPELINE => 0)`
482			`port map (clk => clk, rst => rst,`
483			`a => mantissa_abs_q1,`
484			`arith => neg3(0),`
485			`shft => lzc_q,`
486			`shifted_a => mantissa_lzc_d);`
487
488			`SUB_LZC_EXP :`
489			`exp_add_lzc`
490			`generic map(SIZE_EXP => 6, SIZE_LZC => 5)`
491			`port map (exp_in => exp_int_q5, lzc => lzc_q, exp_out => exp_lzc_d);`
492
493			`-- pipeline register 6`
494			`-- mantissa_lzc, exp_lzc, sign_res`
495			`-- LATCH_MANTISSA_LZC_S6:`
496			`-- d_ff generic map (n => 24)`
497			`-- port map (clk => clk, rst => rst,`
498			`-- d => mantissa_lzc_d, q=>mantissa_lzc_q);`
499
500			`mantissa_lzc_q <= mantissa_lzc_d;`
501			`sign_res4 <= sign_res3;`
502			`exp_lzc_q <= exp_lzc_d;`
503			`res_zero4 <= res_zero3;`
504			`neg4 <= neg3;`
505
506			`--`
507			`-- LATCH_sign_res_S6 : d_ff`
508			`-- generic map (N => 1)`
509			`-- port map (clk => clk, rst => rst,`
510			`-- d=> sign_res3, q => sign_res4);`
511			`--`
512			`-- LATCH_exp_S6 : d_ff`
513			`-- generic map (N => 6)`
514			`-- port map (clk => clk, rst => rst,`
515			`-- d=> exp_lzc_d, q => exp_lzc_q);`
516			`--`
517			`-- LATCH_ZERO_S6: d_ff`
518			`-- generic map(N=>1)`
519			`-- port map(clk => clk, rst =>rst,`
520			`-- d=>res_zero3, q=>res_zero4);`
521
522			`-- LATCH_NEG_S6: d_ff`
523			`-- generic map(N=>1)`
524			`-- port map(clk => clk, rst =>rst,`
525			`-- d=>neg3, q=>neg4);`
526
527			`--rounding`
528			`ROUND:`
529			`round_norm generic map(OPERAND_SIZE => 22,`
530			`MANTISSA_SIZE => 11,`
531			`RND_PREC => 1,`
532			`PIPELINE => 0)`
533			`port map (clk => clk, rst => rst,`
534			`mantissa_in => mantissa_lzc_q,`
535			`mantissa_out => mantissa_res_d,`
536			`neg => neg4(0),`
537			`ovf_norm => ovf_norm,`
538			`ovf_rnd => ovf_round);`
539
540			`EXP_UPDATE:`
541			`exp_add_norm generic map (SIZE_EXP => 6, PIPELINE => 0)`
542			`port map (clk => clk, rst => rst,`
543			`exp_in => exp_lzc_q,`
544			`ovf_norm => ovf_norm,`
545			`ovf_rnd => ovf_round,`
546			`exp_out => exp_res_int);`
547
548			`--PIPELINE_STAGE 6`
549			`-- sign res`
550
551			`-- sign_res5 <= sign_res4;`
552			`sign_res5 <= sign_res4;`
553			`res_zero5 <= res_zero4;`
554
555			`sign_res <= sign_res5(0);`
556			`exp_res <= exp_res_int (4 downto 0) when res_zero5(0) = '0' else`
557			`(others =>'0');`
558			`mantissa_res <= mantissa_res_d when res_zero5(0) = '0' else`
559			`(others => '0');`
560
561
562			`end Behavioral;`
563