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bigsascha3 |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:56:33 02/06/2013
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-- Design Name:
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-- Module Name: lzc_tree - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.math_real.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity lzc_tree is
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generic (SIZE_INT : natural := 42;
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PIPELINE : natural := 2);
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port (clk, rst : in std_logic;
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a : in std_logic_vector(SIZE_INT - 1 downto 0);
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ovf : in std_logic;
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lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));
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end lzc_tree;
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architecture Behavioral of lzc_tree is
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component d_ff
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generic (N: natural := 8);
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port (clk, rst : in std_logic;
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d : in std_logic_vector (N-1 downto 0);
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q : out std_logic_vector (N-1 downto 0));
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end component;
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constant nr_levels : integer := integer (CEIL(LOG2(real (SIZE_INT)))) - 1 ;
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constant max_pow_2 : integer := integer (2.0 ** (CEIL (LOG2 (real (SIZE_INT)))));
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constant size_lz : integer := integer(CEIL(LOG2(real(SIZE_INT))));
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type v_type is array (nr_levels - 1 downto 0) of std_logic_vector(max_pow_2 - 1 downto 0);
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type p_type is array(nr_levels - 1 downto 0) of std_logic_vector (max_pow_2 - 1 downto 0);
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signal a_complete : std_logic_vector(max_pow_2 - 1 downto 0);
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signal v_d, v_q : v_type;
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signal p_d, p_q : p_type;
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signal lzc : std_logic_vector(size_lz - 1 downto 0);
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begin
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a_complete (max_pow_2 - 1 downto max_pow_2 - 1 - SIZE_INT + 1) <= a;
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gen_if:
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if(max_pow_2 /= SIZE_INT) generate
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a_complete (max_pow_2 - 1 - SIZE_INT downto 0) <= (others => '0');
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end generate;
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level_0:
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for i in max_pow_2/4 - 1 downto 0 generate
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v_d(0)(i) <= '0' when a_complete(4*i + 3 downto 4*i) = "0000" else
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'1';
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p_d(0)(2*i+1 downto 2*i) <= "00" when a_complete(4*i+3) = '1' else
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"01" when a_complete(4*i+2) = '1' else
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"10" when a_complete(4*i+1) = '1' else
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"11";
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end generate;
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level_generation:
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for i in 1 to nr_levels - 1 generate
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v_levels:
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for j in 0 to max_pow_2/(integer(2**(i+2))) - 1 generate
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v_d(i)(j) <= v_q(i-1)(2*j+1) or v_q(i-1)(2*j);
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end generate;
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p_levels:
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for j in 0 to max_pow_2/(integer(2**(i+2))) - 1 generate
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p_d(i)((i+2)*j+i+1) <= not(v_q(i-1)(2*j+1));
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p_d(i)((i+2)*j+i downto (i+2)*j) <= p_q(i-1)(j*(2*i+2) + 2*i + 1 downto j*(2*i+2) + i+1) when v_q(i-1)(2*j+1) = '1'
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else p_q(i-1)(j*(2*i+2) + i downto j*(2*i+2));
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end generate;
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end generate;
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pipeline_stages:
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if(PIPELINE /= 0) generate
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INSERTION:
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for i in 0 to nr_levels - 2 generate
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INS: if ((i+1) mod nr_levels/(PIPELINE+1) = 0) generate
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P_Di : D_FF generic map (N => max_pow_2)
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port map( clk => clk, rst => rst,
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d => p_d(i), q =>p_q(i));
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V_Di : D_FF generic map (N => max_pow_2)
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port map( clk => clk, rst => rst,
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d => v_d(i), q =>v_q(i));
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end generate INS;
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NO_INS: if ((i+1) mod nr_levels/(PIPELINE+1) /= 0) generate
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P_ASSIGN: p_q(i) <= p_d(i);
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V_ASSIGN: v_q(i) <= v_d(i);
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end generate NO_INS;
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end generate;
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p_q(nr_levels - 1) <= p_d(nr_levels - 1);
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v_q(nr_levels - 1) <= v_d(nr_levels - 1);
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end generate;
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no_pipeline:
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if(PIPELINE = 0) generate
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NO_INSERTION:
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for i in 0 to nr_levels - 1 generate
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P_ASSIGN_0: p_q(i) <= p_d(i);
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V_ASSIGN_0: v_q(i) <= v_d(i);
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end generate;
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end generate;
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lzc (size_lz - 1 downto 0) <= p_q(nr_levels - 1)(size_lz - 1 downto 0);
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lz_ovf:
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for i in 0 to size_lz - 1 generate
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lz(i) <= lzc (i) and (not ovf);
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end generate;
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end Behavioral;
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