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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:13:48 02/13/2013 
-- Design Name: 
-- Module Name:    sp_mac_loss - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity sp_mac_loss is
        port (clk, rst : in std_logic;
                        mantissa_a, mantissa_b : in std_logic_vector(23 downto 0);
                        mantissa_c : in std_logic_vector (23 downto 0);
                        exp_a, exp_b : in std_logic_vector(7 downto 0);
                        exp_c : in std_logic_vector(7 downto 0);
                        sign_a, sign_b : in std_logic;
                        sign_c : in std_logic;
                        sub : in std_logic;
                        mantissa_res : out std_logic_vector(23 downto 0);
                        exp_res : out std_logic_vector(7 downto 0);
                        sign_res : out std_logic);
end sp_mac_loss;
 
architecture Behavioral of sp_mac_loss is
 
        component exp_add_lzc
                generic( SIZE_EXP : natural := 5;
                                SIZE_LZC : natural := 4);
                port (exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
                                lzc : in std_logic_vector(SIZE_LZC - 1 downto 0);
                                exp_out : out std_logic_vector (SIZE_EXP - 1 downto 0));
        end component;
 
        component exp_add_norm
                generic (SIZE_EXP : natural := 5;
                                PIPELINE : natural := 0);
                port (clk, rst : in std_logic;
                        exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
                        ovf_norm : in std_logic_vector (1 downto 0);
                        ovf_rnd : in std_logic;
                        exp_out : out std_logic_vector(SIZE_EXP - 1 downto 0));
        end component;
 
        component sign_comp
                port (sign_a, sign_b : in std_logic;
                        sign_c : in std_logic;
                        comp_exp : in std_logic;
                        eff_sub : in std_logic;
                        sign_add : in std_logic;
                        sign_res : out std_logic);
        end component;
 
        component exponent_align
                generic (SIZE_EXP : natural := 5;
                                        PIPELINE : natural := 2); -- nr of pipeline registers -- max 2
                port (clk, rst : in std_logic;
                                exp_a, exp_b : in std_logic_vector (SIZE_EXP - 1 downto 0);
                                exp_c : in std_logic_vector (SIZE_EXP - 1 downto 0);
                                align : out std_logic_vector (SIZE_EXP - 1 downto 0);
                                exp_int : out std_logic_vector (SIZE_EXP downto 0);
                                comp : out std_logic);
        end component;
 
        component effective_op is
                port (sign_a, sign_b, sign_c : in std_logic;
                        sub: in std_logic;
                        eff_sub : out std_logic);
        end component;
 
        component shift
                generic (INPUT_SIZE : natural := 13;
                                SHIFT_SIZE : natural := 4;
                                OUTPUT_SIZE : natural := 24;
                                DIRECTION : natural := 1;  -- 1 for left shift; 0 for right shift
                                PIPELINE : natural := 1;
                                POSITION : std_logic_vector(7 downto 0) := "00000000"); -- number of pipeline registers
                port (clk, rst : in std_logic;
                        a : in std_logic_vector (INPUT_SIZE - 1 downto 0);
                        arith : in std_logic;
                        shft : in std_logic_vector (SHIFT_SIZE - 1 downto 0);
                        shifted_a : out std_logic_vector (OUTPUT_SIZE - 1 downto 0));
        end component;
 
        component round_norm
                generic ( OPERAND_SIZE : natural := 24;
                                MANTISSA_SIZE : natural := 12;
                                RND_PREC : natural := 0; --0 RNE, 1 Trunc
                                PIPELINE: natural := 1); -- 0 - no pipeline
                port ( clk, rst : std_logic;
                        mantissa_in : in std_logic_vector (OPERAND_SIZE + 1 downto 0);
                        mantissa_out: out std_logic_vector (MANTISSA_SIZE - 1 downto 0);
                        neg : in std_logic;
                        ovf_norm : out std_logic_vector(1 downto 0);
                        ovf_rnd : out std_logic);
        end component;
 
        component dsp_unit_sp
                port (clk, rst : in std_logic;
                        a : in std_logic_vector(33 downto 0);
                        b : in std_logic_vector(23 downto 0);
                        c:  in std_logic_vector(71 downto 0);
                        comp : in std_logic;  -- 1 a*b > c; 0 a*b <= c
                        sub : in std_logic;  --
                        p1: out std_logic_vector (47 downto 0);
                        p2: out std_logic_vector (48 downto 0);
                        pattern_detect : out std_logic);
        end component;
 
        component d_ff
                generic (N: natural := 8);
                port (clk, rst : in std_logic;
                                d : in std_logic_vector (N-1 downto 0);
                                q : out std_logic_vector (N-1 downto 0));
        end component;
 
        component lzc_tree
                generic (SIZE_INT : natural := 42;
                                PIPELINE : natural := 2);
                port (clk, rst : in std_logic;
                        a  : in std_logic_vector(SIZE_INT - 1 downto 0);
                        ovf : in std_logic;
                        lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));
        end component;
 
        signal mantissa_a_q, mantissa_b_q, mantissa_c_q : std_logic_vector(23 downto 0);
        signal mantissa_b_q0 : std_logic_vector(23 downto 0);
 
        signal eff_sub : std_logic;
        signal comp : std_logic;
        signal sub_vec : std_logic_vector(0 downto 0);
        signal comp_vec : std_logic_vector(0 downto 0);
        signal sub_dsp : std_logic_vector(0 downto 0);
        signal sub_vec0 : std_logic_vector(0 downto 0);
        signal comp_vec0 : std_logic_vector(0 downto 0);
        signal sub_vec1 : std_logic_vector(0 downto 0);
        signal comp_vec1 : std_logic_vector(0 downto 0);
        signal sub_dsp0 : std_logic_vector(0 downto 0);
        signal comp_dsp : std_logic_vector(0 downto 0);
        signal sub_dsp1 : std_logic_vector(0 downto 0);
        signal comp_dsp1 : std_logic_vector(0 downto 0);
        signal sub_dsp2 : std_logic_vector(0 downto 0);
        signal comp_dsp2 : std_logic_vector(0 downto 0);
        signal sub_dsp3 : std_logic_vector(0 downto 0);
        signal comp_dsp3 : std_logic_vector(0 downto 0);
        signal sign_d : std_logic_vector (2 downto 0);
        signal sign_q : std_logic_vector (2 downto 0);
        signal sign_q0 : std_logic_vector (2 downto 0);
        signal sign_q1 : std_logic_vector (2 downto 0);
        signal sign_q2 : std_logic_vector (2 downto 0);
        signal sign_q3 : std_logic_vector (2 downto 0);
        signal sign_q4 : std_logic_vector (2 downto 0);
        signal sign_mantissa_add : std_logic;
        signal sign_res1 : std_logic_vector(0 downto 0);
        signal sign_res2 : std_logic_vector(0 downto 0);
        signal sign_res3 : std_logic_vector(0 downto 0);
        signal sign_res4 : std_logic_vector(0 downto 0);
        signal sign_res5 : std_logic_vector(0 downto 0);
        signal sign_res6 : std_logic_vector(0 downto 0);
 
 
        signal align_d, align_q : std_logic_vector(7 downto 0);
        signal exp_int : std_logic_vector(8 downto 0);
        signal exp_int_q0 : std_logic_vector (8 downto 0);
        signal exp_int_q1 : std_logic_vector(8 downto 0);
        signal exp_int_q2 : std_logic_vector(8 downto 0);
        signal exp_int_q3 : std_logic_vector(8 downto 0);
        signal exp_int_q4 : std_logic_vector(8 downto 0);
        signal exp_int_q5 : std_logic_vector(8 downto 0);
        signal exp_int_q6 : std_logic_vector(8 downto 0);
        signal exp_lzc_d, exp_lzc_q : std_logic_vector (8 downto 0);
        signal exp_res_int : std_logic_vector (8 downto 0);
 
        signal align_a_d : std_logic_vector(4 downto 0);
        signal align_c_d : std_logic_vector(5 downto 0);
        signal align_a : std_logic_vector(4 downto 0);
        signal align_c : std_logic_vector(5 downto 0);
 
        signal aligned_mantissa_a : std_logic_vector(33 downto 0);
        signal aligned_mantissa_c_d : std_logic_vector(71 downto 0);
        signal aligned_mantissa_c_q : std_logic_vector(71 downto 0);
 
        signal p1 : std_logic_vector(47 downto 0);
        signal p2 : std_logic_vector(48 downto 0);
        signal p : std_logic_vector(60 downto 0);
        signal p_q : std_logic_vector(60 downto 0);
        signal mantissa_abs_d : std_logic_vector(59 downto 0);
        signal mantissa_abs_q1 : std_logic_vector(59 downto 0);
        signal mantissa_abs_q2 : std_logic_vector(59 downto 0);
        signal mantissa_lzc_d : std_logic_vector(59 downto 0);
        signal mantissa_lzc_q : std_logic_vector(59 downto 0);
        signal mantissa_res_d: std_logic_vector (23 downto 0);
 
        signal ovf_round: std_logic;
        signal ovf_norm : std_logic_vector (1 downto 0);
 
        signal ovf_mac : std_logic;
 
        signal lzc_d, lzc_q : std_logic_vector(5 downto 0);
        signal zero : std_logic:= '0';
 
        signal add_msbs_p : std_logic_vector(60 downto 0);
        signal add_lsbs_p : std_logic_vector(60 downto 0);
 
begin
 
        --STAGE 1
 
        EFFECTIVE_SUB:
                effective_op port map (sign_a => sign_a, sign_b => sign_b, sign_c => sign_c,
                                                                sub => sub, eff_sub => eff_sub);
 
        EXP_ALIGN : exponent_align
                                                generic map (SIZE_EXP => 8, PIPELINE => 1)
                                                port map (clk => clk, rst => rst,
                                                        exp_a => exp_a, exp_b => exp_b,
                                                        exp_c => exp_c, align => align_d,
                                                        exp_int => exp_int, comp=>comp);
 
 
        sub_vec(0) <= eff_sub;
        comp_vec(0) <= comp;
 
        sign_d(0) <= sign_c;
        sign_d(1) <= sign_b;
        sign_d(2) <= sign_a;
 
        --first stage pipeline
 
        S0_mantissa_a : d_ff
                                        generic map(N=>24)
                                        port map (clk => clk, rst => rst,
                                        d=> mantissa_a, q => mantissa_a_q);
 
        S0_mantissa_b : d_ff
                                        generic map(N=>24)
                                        port map (clk => clk, rst => rst,
                                        d=> mantissa_b, q => mantissa_b_q);
 
        S0_mantissa_c : d_ff
                                        generic map(N=>24)
                                        port map (clk => clk, rst => rst,
                                        d=> mantissa_c, q => mantissa_c_q);
 
        LATCH_sub_S0: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_vec, q => sub_vec0);
 
        LATCH_comp_S0: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_vec, q => comp_vec0);
 
        LATCH_sign_S0 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_d, q => sign_q);
 
        --end of 
 
        align_a_d(3 downto 0) <= align_d(3 downto 0) when comp_vec(0) = '0' else
                                                (others => '0');
 
        align_a_d(4) <= (align_d(4) or align_d(5) or align_d(6) or align_d(7)) when comp_vec(0) = '0' else
                                                '0';
 
        align_c_d(4 downto 0) <= align_d (4 downto 0) when comp_vec(0) = '1' else
                                                (others => '0');
 
        align_c_d(5) <= (align_d(5) or align_d(6) or align_d(7)) when comp_vec(0) = '1' else
                                                '0';
 
        align_a(0) <= align_a_d(0);
        align_c(0) <= align_c_d(0);
 
 
        -- second stage pipeline
        S1_exp_int : d_ff
                                        generic map(N => 9)
                                        port map (clk => clk, rst => rst,
                                        d => exp_int, q => exp_int_q0);
 
        S1_mantissa_b : d_ff
                                        generic map(N=>24)
                                        port map (clk => clk, rst => rst,
                                        d=> mantissa_b_q, q => mantissa_b_q0);
 
 
        LATCH_sub_S1: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_vec, q => sub_vec1);
 
        LATCH_comp_S1: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_vec, q => comp_vec1);
 
        LATCH_sign_S1 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q, q => sign_q0);
 
 
        LATCH_align_c : d_ff
                                        generic map (N => 5)
                                        port map (clk => clk, rst => rst,
                                                                d=> align_c_d(5 downto 1), q => align_c(5 downto 1));
 
        LATCH_align_a : d_ff
                                        generic map (N => 4)
                                        port map (clk => clk, rst => rst,
                                                                d=> align_a_d(4 downto 1), q => align_a(4 downto 1));
 
        --end of pipeline
 
        SHIFT_A : shift
                                        generic map (INPUT_SIZE => 24,
                                                                        SHIFT_SIZE => 5,
                                                                        OUTPUT_SIZE => 34,
                                                                        DIRECTION => 0,
                                                                        PIPELINE => 1,
                                                                        POSITION => "00000001")
                                        port map (clk => clk, rst => rst,
                                                        a => mantissa_a_q,
                                                        shft => align_a(4 downto 0),
                                                        arith => zero,
                                                        shifted_a => aligned_mantissa_a);
 
        SHIFT_C : shift
                                        generic map (INPUT_SIZE => 24,
                                                                        SHIFT_SIZE => 6,
                                                                        OUTPUT_SIZE => 58,
                                                                        DIRECTION => 0,
                                                                        PIPELINE => 1,
                                                                        POSITION => "00000001")
                                        port map (clk => clk, rst => rst,
                                                        a => mantissa_c_q,
                                                        shft => align_c (5 downto 0),
                                                        arith => zero,
                                                        shifted_a => aligned_mantissa_c_d (57 downto 0));
 
        aligned_mantissa_c_d (71 downto 58) <= (others => '0');
 
 
 
 
        -- first pipeline register 
-- latching mantissa_c, sub_eff, comp, exp_int, signs 
-- a and b are latched inside the dsp block     
 
 
 
        LATCH_C_S2: d_ff
                                        generic map ( N => 72)
                                        port map (clk => clk, rst => rst,
                                                        d => aligned_mantissa_c_d, q => aligned_mantissa_c_q);
        LATCH_sub_S2: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_vec1, q => sub_dsp);
 
        LATCH_comp_S2: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_vec1, q => comp_dsp);
 
        LATCH_sign_S2 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q0, q => sign_q1);
 
        LATCH_exp_S2 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q0, q => exp_int_q1);
 
 -- instantiating the DSP
        DSP:
                dsp_unit_sp
                        port map(clk => clk, rst => rst,
                        a => aligned_mantissa_a,--"00"&x"00000001",--"00"&x"00800000",--
                        b => mantissa_b_q0,--x"000001",--x"800000",--
                        c => aligned_mantissa_c_q,--x"000000000000000001",--x"000000000000800000",--
                        comp => comp_dsp(0),  -- 1 a*b > c; 0 a*b <= c
                        sub => sub_dsp(0),  --
                        p1 => p1,
                        p2 => p2,
                        pattern_detect => open);
 
--pipeline statges outside the dsp
        LATCH_sub_S3: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_dsp, q => sub_dsp1);
 
        LATCH_comp_S3: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_dsp, q => comp_dsp1);
 
        LATCH_sign_S3 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q1, q => sign_q2);
 
        LATCH_exp_S3 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q1, q => exp_int_q2);
 
        LATCH_sub_S4: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_dsp1, q => sub_dsp2);
 
        LATCH_comp_S4: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_dsp1, q => comp_dsp2);
 
        LATCH_sign_S4 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q2, q => sign_q3);
 
        LATCH_exp_S4 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q2, q => exp_int_q3);
 
        --computing the mantissa mac
 
        --add_msbs_p <= (60 downto 48 => '0') & p1;
        --add_lsbs_p <= p2(43 downto 0) & (16 downto 0=>'0');
 
        add_msbs_p <= p1(43 downto 0) & (16 downto 0=>'0');
        add_lsbs_p <= (60 downto 48 => '0') & p2(47 downto 0);
        p <= add_msbs_p + add_lsbs_p;
 
        --latching the result
 
        LATCH_sub_S5: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> sub_dsp2, q => sub_dsp3);
 
        LATCH_comp_S5: d_ff
                                        generic map ( N => 1)
                                        port map ( clk => clk, rst => rst,
                                                                d=> comp_dsp2, q => comp_dsp3);
 
        LATCH_sign_S5 : d_ff
                                        generic map (N => 3)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_q3, q => sign_q4);
 
        LATCH_exp_S5 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q3, q => exp_int_q4);
 
        LATCH_p_S5 :    d_ff
                                        generic map(N=>61)
                                        port map (clk => clk, rst => rst,
                                                        d => p, q => p_q);
 
        -- absolute value
        sign_mantissa_add <= p_q(60);
 
        mantissa_abs_d <= p_q (59 downto 0) when sign_mantissa_add = '0' else
                                                        -(p_q(59 downto 0));
 
        SIGN_RESULT_COMP :
                        sign_comp
                                port map(sign_a => sign_q4(2), sign_b => sign_q4(1),
                                        sign_c => sign_q4(0),
                                        comp_exp => comp_dsp3(0),
                                        eff_sub => sub_dsp3(0),
                                        sign_add => sign_mantissa_add,
                                        sign_res => sign_res1(0));
 
-- Fifth PIPELINE REGISTERS
        -- abs value of mantissa, exp_int, sign_res
        LATCH_MANTISSA_ABS_S6:
                d_ff generic map (n => 60)
                                port map (clk => clk, rst => rst,
                                                        d => mantissa_abs_d, q=>mantissa_abs_q1);
 
        LATCH_sign_res_S6 : d_ff
                                        generic map (N => 1)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_res1, q => sign_res2);
 
        LATCH_exp_S6 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q4, q => exp_int_q5);
 
        --pipeline stage
        ovf_mac <= mantissa_abs_q1(59) or mantissa_abs_q1(58);
        LZC_COUNT : lzc_tree
                                        generic map ( SIZE_INT => 58,
                                                                                PIPELINE => 0)
                                        port map (clk => clk, rst => rst,
                                                                a => mantissa_abs_q1(57 downto 0),
                                                                ovf => ovf_mac, lz => lzc_d);
   --pipeline_registers
        LATCH_MANTISSA_ABS_S7:
                d_ff generic map (n => 60)
                                port map (clk => clk, rst => rst,
                                                        d => mantissa_abs_q1, q=>mantissa_abs_q2);
 
        LATCH_sign_res_S7 : d_ff
                                        generic map (N => 1)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_res2, q => sign_res3);
 
        LATCH_exp_S7 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_int_q5, q => exp_int_q6);
 
        LATCH_lzc_S7 : d_ff
                                        generic map (N => 6)
                                        port map (clk => clk, rst => rst,
                                                                d=> lzc_d, q => lzc_q);
 
        -- another stage
 
        SHIFT_MANTISSA : shift
                                                generic map (INPUT_SIZE => 60,
                                                                                SHIFT_SIZE => 6,
                                                                                OUTPUT_SIZE => 60,
                                                                                DIRECTION => 1,
                                                                                PIPELINE => 0)
                                                port map (clk => clk, rst => rst,
                                                                a => mantissa_abs_q2,
                                                                shft => lzc_q,
                                                                shifted_a => mantissa_lzc_d,
                                                                arith => zero);
 
        SUB_LZC_EXP :
                exp_add_lzc
                        generic map(SIZE_EXP => 9, SIZE_LZC => 6)
                        port map (exp_in => exp_int_q6, lzc => lzc_q, exp_out => exp_lzc_d);
 
 
        -- pipeline register 7
        -- mantissa_lzc, exp_lzc, sign_res
        LATCH_MANTISSA_LZC_S8:
                                d_ff generic map (n => 60)
                                                port map (clk => clk, rst => rst,
                                                                        d => mantissa_lzc_d, q=>mantissa_lzc_q);
 
        LATCH_sign_res_S8 : d_ff
                                        generic map (N => 1)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_res3, q => sign_res4);
 
        LATCH_exp_S8 : d_ff
                                        generic map (N => 9)
                                        port map (clk => clk, rst => rst,
                                                                d=> exp_lzc_d, q => exp_lzc_q);
 
        --rounding
        ROUND:
                round_norm generic map(OPERAND_SIZE => 58,
                                                                                MANTISSA_SIZE => 24,
                                                                                RND_PREC => 0,
                                                                                PIPELINE => 1)
                                                port map (clk => clk, rst => rst,
                                                                        mantissa_in => mantissa_lzc_q,
                                                                        mantissa_out => mantissa_res_d,
                                                                        ovf_norm => ovf_norm,
                                                                        neg => zero,
                                                                        ovf_rnd => ovf_round);
 
        EXP_UPDATE:
                exp_add_norm generic map (SIZE_EXP => 9, PIPELINE => 1)
                                                port map (clk => clk, rst => rst,
                                                        exp_in => exp_lzc_q,
                                                        ovf_norm => ovf_norm,
                                                        ovf_rnd => ovf_round,
                                                        exp_out => exp_res_int);
 
        --PIPELINE STAGE 6
        -- sign res
                LATCH_sign_res_S9 : d_ff
                                        generic map (N => 1)
                                        port map (clk => clk, rst => rst,
                                                                d=> sign_res4, q => sign_res5);
 
 
                sign_res <= sign_res5(0);
                exp_res <= exp_res_int (7 downto 0);
                mantissa_res <= mantissa_res_d;
 
 
end Behavioral;
 

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[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePrecision/] [sp_mac_loss.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	bigsascha3	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 16:13:48 02/13/2013`
6			`-- Design Name:`
7			`-- Module Name: sp_mac_loss - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.std_logic_signed.all;`
23			`use IEEE.std_logic_arith.all;`
24			`use IEEE.math_real.all;`
25
26			`-- Uncomment the following library declaration if using`
27			`-- arithmetic functions with Signed or Unsigned values`
28			`--use IEEE.NUMERIC_STD.ALL;`
29
30			`-- Uncomment the following library declaration if instantiating`
31			`-- any Xilinx primitives in this code.`
32			`--library UNISIM;`
33			`--use UNISIM.VComponents.all;`
34
35			`entity sp_mac_loss is`
36			`port (clk, rst : in std_logic;`
37			`mantissa_a, mantissa_b : in std_logic_vector(23 downto 0);`
38			`mantissa_c : in std_logic_vector (23 downto 0);`
39			`exp_a, exp_b : in std_logic_vector(7 downto 0);`
40			`exp_c : in std_logic_vector(7 downto 0);`
41			`sign_a, sign_b : in std_logic;`
42			`sign_c : in std_logic;`
43			`sub : in std_logic;`
44			`mantissa_res : out std_logic_vector(23 downto 0);`
45			`exp_res : out std_logic_vector(7 downto 0);`
46			`sign_res : out std_logic);`
47			`end sp_mac_loss;`
48
49			`architecture Behavioral of sp_mac_loss is`
50
51			`component exp_add_lzc`
52			`generic( SIZE_EXP : natural := 5;`
53			`SIZE_LZC : natural := 4);`
54			`port (exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);`
55			`lzc : in std_logic_vector(SIZE_LZC - 1 downto 0);`
56			`exp_out : out std_logic_vector (SIZE_EXP - 1 downto 0));`
57			`end component;`
58
59			`component exp_add_norm`
60			`generic (SIZE_EXP : natural := 5;`
61			`PIPELINE : natural := 0);`
62			`port (clk, rst : in std_logic;`
63			`exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);`
64			`ovf_norm : in std_logic_vector (1 downto 0);`
65			`ovf_rnd : in std_logic;`
66			`exp_out : out std_logic_vector(SIZE_EXP - 1 downto 0));`
67			`end component;`
68
69			`component sign_comp`
70			`port (sign_a, sign_b : in std_logic;`
71			`sign_c : in std_logic;`
72			`comp_exp : in std_logic;`
73			`eff_sub : in std_logic;`
74			`sign_add : in std_logic;`
75			`sign_res : out std_logic);`
76			`end component;`
77
78			`component exponent_align`
79			`generic (SIZE_EXP : natural := 5;`
80			`PIPELINE : natural := 2); -- nr of pipeline registers -- max 2`
81			`port (clk, rst : in std_logic;`
82			`exp_a, exp_b : in std_logic_vector (SIZE_EXP - 1 downto 0);`
83			`exp_c : in std_logic_vector (SIZE_EXP - 1 downto 0);`
84			`align : out std_logic_vector (SIZE_EXP - 1 downto 0);`
85			`exp_int : out std_logic_vector (SIZE_EXP downto 0);`
86			`comp : out std_logic);`
87			`end component;`
88
89			`component effective_op is`
90			`port (sign_a, sign_b, sign_c : in std_logic;`
91			`sub: in std_logic;`
92			`eff_sub : out std_logic);`
93			`end component;`
94
95			`component shift`
96			`generic (INPUT_SIZE : natural := 13;`
97			`SHIFT_SIZE : natural := 4;`
98			`OUTPUT_SIZE : natural := 24;`
99			`DIRECTION : natural := 1; -- 1 for left shift; 0 for right shift`
100			`PIPELINE : natural := 1;`
101			`POSITION : std_logic_vector(7 downto 0) := "00000000"); -- number of pipeline registers`
102			`port (clk, rst : in std_logic;`
103			`a : in std_logic_vector (INPUT_SIZE - 1 downto 0);`
104			`arith : in std_logic;`
105			`shft : in std_logic_vector (SHIFT_SIZE - 1 downto 0);`
106			`shifted_a : out std_logic_vector (OUTPUT_SIZE - 1 downto 0));`
107			`end component;`
108
109			`component round_norm`
110			`generic ( OPERAND_SIZE : natural := 24;`
111			`MANTISSA_SIZE : natural := 12;`
112			`RND_PREC : natural := 0; --0 RNE, 1 Trunc`
113			`PIPELINE: natural := 1); -- 0 - no pipeline`
114			`port ( clk, rst : std_logic;`
115			`mantissa_in : in std_logic_vector (OPERAND_SIZE + 1 downto 0);`
116			`mantissa_out: out std_logic_vector (MANTISSA_SIZE - 1 downto 0);`
117			`neg : in std_logic;`
118			`ovf_norm : out std_logic_vector(1 downto 0);`
119			`ovf_rnd : out std_logic);`
120			`end component;`
121
122			`component dsp_unit_sp`
123			`port (clk, rst : in std_logic;`
124			`a : in std_logic_vector(33 downto 0);`
125			`b : in std_logic_vector(23 downto 0);`
126			`c: in std_logic_vector(71 downto 0);`
127			`comp : in std_logic; -- 1 ab > c; 0 ab <= c`
128			`sub : in std_logic; --`
129			`p1: out std_logic_vector (47 downto 0);`
130			`p2: out std_logic_vector (48 downto 0);`
131			`pattern_detect : out std_logic);`
132			`end component;`
133
134			`component d_ff`
135			`generic (N: natural := 8);`
136			`port (clk, rst : in std_logic;`
137			`d : in std_logic_vector (N-1 downto 0);`
138			`q : out std_logic_vector (N-1 downto 0));`
139			`end component;`
140
141			`component lzc_tree`
142			`generic (SIZE_INT : natural := 42;`
143			`PIPELINE : natural := 2);`
144			`port (clk, rst : in std_logic;`
145			`a : in std_logic_vector(SIZE_INT - 1 downto 0);`
146			`ovf : in std_logic;`
147			`lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));`
148			`end component;`
149
150			`signal mantissa_a_q, mantissa_b_q, mantissa_c_q : std_logic_vector(23 downto 0);`
151			`signal mantissa_b_q0 : std_logic_vector(23 downto 0);`
152
153			`signal eff_sub : std_logic;`
154			`signal comp : std_logic;`
155			`signal sub_vec : std_logic_vector(0 downto 0);`
156			`signal comp_vec : std_logic_vector(0 downto 0);`
157			`signal sub_dsp : std_logic_vector(0 downto 0);`
158			`signal sub_vec0 : std_logic_vector(0 downto 0);`
159			`signal comp_vec0 : std_logic_vector(0 downto 0);`
160			`signal sub_vec1 : std_logic_vector(0 downto 0);`
161			`signal comp_vec1 : std_logic_vector(0 downto 0);`
162			`signal sub_dsp0 : std_logic_vector(0 downto 0);`
163			`signal comp_dsp : std_logic_vector(0 downto 0);`
164			`signal sub_dsp1 : std_logic_vector(0 downto 0);`
165			`signal comp_dsp1 : std_logic_vector(0 downto 0);`
166			`signal sub_dsp2 : std_logic_vector(0 downto 0);`
167			`signal comp_dsp2 : std_logic_vector(0 downto 0);`
168			`signal sub_dsp3 : std_logic_vector(0 downto 0);`
169			`signal comp_dsp3 : std_logic_vector(0 downto 0);`
170			`signal sign_d : std_logic_vector (2 downto 0);`
171			`signal sign_q : std_logic_vector (2 downto 0);`
172			`signal sign_q0 : std_logic_vector (2 downto 0);`
173			`signal sign_q1 : std_logic_vector (2 downto 0);`
174			`signal sign_q2 : std_logic_vector (2 downto 0);`
175			`signal sign_q3 : std_logic_vector (2 downto 0);`
176			`signal sign_q4 : std_logic_vector (2 downto 0);`
177			`signal sign_mantissa_add : std_logic;`
178			`signal sign_res1 : std_logic_vector(0 downto 0);`
179			`signal sign_res2 : std_logic_vector(0 downto 0);`
180			`signal sign_res3 : std_logic_vector(0 downto 0);`
181			`signal sign_res4 : std_logic_vector(0 downto 0);`
182			`signal sign_res5 : std_logic_vector(0 downto 0);`
183			`signal sign_res6 : std_logic_vector(0 downto 0);`
184
185
186			`signal align_d, align_q : std_logic_vector(7 downto 0);`
187			`signal exp_int : std_logic_vector(8 downto 0);`
188			`signal exp_int_q0 : std_logic_vector (8 downto 0);`
189			`signal exp_int_q1 : std_logic_vector(8 downto 0);`
190			`signal exp_int_q2 : std_logic_vector(8 downto 0);`
191			`signal exp_int_q3 : std_logic_vector(8 downto 0);`
192			`signal exp_int_q4 : std_logic_vector(8 downto 0);`
193			`signal exp_int_q5 : std_logic_vector(8 downto 0);`
194			`signal exp_int_q6 : std_logic_vector(8 downto 0);`
195			`signal exp_lzc_d, exp_lzc_q : std_logic_vector (8 downto 0);`
196			`signal exp_res_int : std_logic_vector (8 downto 0);`
197
198			`signal align_a_d : std_logic_vector(4 downto 0);`
199			`signal align_c_d : std_logic_vector(5 downto 0);`
200			`signal align_a : std_logic_vector(4 downto 0);`
201			`signal align_c : std_logic_vector(5 downto 0);`
202
203			`signal aligned_mantissa_a : std_logic_vector(33 downto 0);`
204			`signal aligned_mantissa_c_d : std_logic_vector(71 downto 0);`
205			`signal aligned_mantissa_c_q : std_logic_vector(71 downto 0);`
206
207			`signal p1 : std_logic_vector(47 downto 0);`
208			`signal p2 : std_logic_vector(48 downto 0);`
209			`signal p : std_logic_vector(60 downto 0);`
210			`signal p_q : std_logic_vector(60 downto 0);`
211			`signal mantissa_abs_d : std_logic_vector(59 downto 0);`
212			`signal mantissa_abs_q1 : std_logic_vector(59 downto 0);`
213			`signal mantissa_abs_q2 : std_logic_vector(59 downto 0);`
214			`signal mantissa_lzc_d : std_logic_vector(59 downto 0);`
215			`signal mantissa_lzc_q : std_logic_vector(59 downto 0);`
216			`signal mantissa_res_d: std_logic_vector (23 downto 0);`
217
218			`signal ovf_round: std_logic;`
219			`signal ovf_norm : std_logic_vector (1 downto 0);`
220
221			`signal ovf_mac : std_logic;`
222
223			`signal lzc_d, lzc_q : std_logic_vector(5 downto 0);`
224			`signal zero : std_logic:= '0';`
225
226			`signal add_msbs_p : std_logic_vector(60 downto 0);`
227			`signal add_lsbs_p : std_logic_vector(60 downto 0);`
228
229			`begin`
230
231			`--STAGE 1`
232
233			`EFFECTIVE_SUB:`
234			`effective_op port map (sign_a => sign_a, sign_b => sign_b, sign_c => sign_c,`
235			`sub => sub, eff_sub => eff_sub);`
236
237			`EXP_ALIGN : exponent_align`
238			`generic map (SIZE_EXP => 8, PIPELINE => 1)`
239			`port map (clk => clk, rst => rst,`
240			`exp_a => exp_a, exp_b => exp_b,`
241			`exp_c => exp_c, align => align_d,`
242			`exp_int => exp_int, comp=>comp);`
243
244
245			`sub_vec(0) <= eff_sub;`
246			`comp_vec(0) <= comp;`
247
248			`sign_d(0) <= sign_c;`
249			`sign_d(1) <= sign_b;`
250			`sign_d(2) <= sign_a;`
251
252			`--first stage pipeline`
253
254			`S0_mantissa_a : d_ff`
255			`generic map(N=>24)`
256			`port map (clk => clk, rst => rst,`
257			`d=> mantissa_a, q => mantissa_a_q);`
258
259			`S0_mantissa_b : d_ff`
260			`generic map(N=>24)`
261			`port map (clk => clk, rst => rst,`
262			`d=> mantissa_b, q => mantissa_b_q);`
263
264			`S0_mantissa_c : d_ff`
265			`generic map(N=>24)`
266			`port map (clk => clk, rst => rst,`
267			`d=> mantissa_c, q => mantissa_c_q);`
268
269			`LATCH_sub_S0: d_ff`
270			`generic map ( N => 1)`
271			`port map ( clk => clk, rst => rst,`
272			`d=> sub_vec, q => sub_vec0);`
273
274			`LATCH_comp_S0: d_ff`
275			`generic map ( N => 1)`
276			`port map ( clk => clk, rst => rst,`
277			`d=> comp_vec, q => comp_vec0);`
278
279			`LATCH_sign_S0 : d_ff`
280			`generic map (N => 3)`
281			`port map (clk => clk, rst => rst,`
282			`d=> sign_d, q => sign_q);`
283
284			`--end of`
285
286			`align_a_d(3 downto 0) <= align_d(3 downto 0) when comp_vec(0) = '0' else`
287			`(others => '0');`
288
289			`align_a_d(4) <= (align_d(4) or align_d(5) or align_d(6) or align_d(7)) when comp_vec(0) = '0' else`
290			`'0';`
291
292			`align_c_d(4 downto 0) <= align_d (4 downto 0) when comp_vec(0) = '1' else`
293			`(others => '0');`
294
295			`align_c_d(5) <= (align_d(5) or align_d(6) or align_d(7)) when comp_vec(0) = '1' else`
296			`'0';`
297
298			`align_a(0) <= align_a_d(0);`
299			`align_c(0) <= align_c_d(0);`
300
301
302			`-- second stage pipeline`
303			`S1_exp_int : d_ff`
304			`generic map(N => 9)`
305			`port map (clk => clk, rst => rst,`
306			`d => exp_int, q => exp_int_q0);`
307
308			`S1_mantissa_b : d_ff`
309			`generic map(N=>24)`
310			`port map (clk => clk, rst => rst,`
311			`d=> mantissa_b_q, q => mantissa_b_q0);`
312
313
314			`LATCH_sub_S1: d_ff`
315			`generic map ( N => 1)`
316			`port map ( clk => clk, rst => rst,`
317			`d=> sub_vec, q => sub_vec1);`
318
319			`LATCH_comp_S1: d_ff`
320			`generic map ( N => 1)`
321			`port map ( clk => clk, rst => rst,`
322			`d=> comp_vec, q => comp_vec1);`
323
324			`LATCH_sign_S1 : d_ff`
325			`generic map (N => 3)`
326			`port map (clk => clk, rst => rst,`
327			`d=> sign_q, q => sign_q0);`
328
329
330			`LATCH_align_c : d_ff`
331			`generic map (N => 5)`
332			`port map (clk => clk, rst => rst,`
333			`d=> align_c_d(5 downto 1), q => align_c(5 downto 1));`
334
335			`LATCH_align_a : d_ff`
336			`generic map (N => 4)`
337			`port map (clk => clk, rst => rst,`
338			`d=> align_a_d(4 downto 1), q => align_a(4 downto 1));`
339
340			`--end of pipeline`
341
342			`SHIFT_A : shift`
343			`generic map (INPUT_SIZE => 24,`
344			`SHIFT_SIZE => 5,`
345			`OUTPUT_SIZE => 34,`
346			`DIRECTION => 0,`
347			`PIPELINE => 1,`
348			`POSITION => "00000001")`
349			`port map (clk => clk, rst => rst,`
350			`a => mantissa_a_q,`
351			`shft => align_a(4 downto 0),`
352			`arith => zero,`
353			`shifted_a => aligned_mantissa_a);`
354
355			`SHIFT_C : shift`
356			`generic map (INPUT_SIZE => 24,`
357			`SHIFT_SIZE => 6,`
358			`OUTPUT_SIZE => 58,`
359			`DIRECTION => 0,`
360			`PIPELINE => 1,`
361			`POSITION => "00000001")`
362			`port map (clk => clk, rst => rst,`
363			`a => mantissa_c_q,`
364			`shft => align_c (5 downto 0),`
365			`arith => zero,`
366			`shifted_a => aligned_mantissa_c_d (57 downto 0));`
367
368			`aligned_mantissa_c_d (71 downto 58) <= (others => '0');`
369
370
371
372
373			`-- first pipeline register`
374			`-- latching mantissa_c, sub_eff, comp, exp_int, signs`
375			`-- a and b are latched inside the dsp block`
376
377
378
379			`LATCH_C_S2: d_ff`
380			`generic map ( N => 72)`
381			`port map (clk => clk, rst => rst,`
382			`d => aligned_mantissa_c_d, q => aligned_mantissa_c_q);`
383			`LATCH_sub_S2: d_ff`
384			`generic map ( N => 1)`
385			`port map ( clk => clk, rst => rst,`
386			`d=> sub_vec1, q => sub_dsp);`
387
388			`LATCH_comp_S2: d_ff`
389			`generic map ( N => 1)`
390			`port map ( clk => clk, rst => rst,`
391			`d=> comp_vec1, q => comp_dsp);`
392
393			`LATCH_sign_S2 : d_ff`
394			`generic map (N => 3)`
395			`port map (clk => clk, rst => rst,`
396			`d=> sign_q0, q => sign_q1);`
397
398			`LATCH_exp_S2 : d_ff`
399			`generic map (N => 9)`
400			`port map (clk => clk, rst => rst,`
401			`d=> exp_int_q0, q => exp_int_q1);`
402
403			`-- instantiating the DSP`
404			`DSP:`
405			`dsp_unit_sp`
406			`port map(clk => clk, rst => rst,`
407			`a => aligned_mantissa_a,--"00"&x"00000001",--"00"&x"00800000",--`
408			`b => mantissa_b_q0,--x"000001",--x"800000",--`
409			`c => aligned_mantissa_c_q,--x"000000000000000001",--x"000000000000800000",--`
410			`comp => comp_dsp(0), -- 1 ab > c; 0 ab <= c`
411			`sub => sub_dsp(0), --`
412			`p1 => p1,`
413			`p2 => p2,`
414			`pattern_detect => open);`
415
416			`--pipeline statges outside the dsp`
417			`LATCH_sub_S3: d_ff`
418			`generic map ( N => 1)`
419			`port map ( clk => clk, rst => rst,`
420			`d=> sub_dsp, q => sub_dsp1);`
421
422			`LATCH_comp_S3: d_ff`
423			`generic map ( N => 1)`
424			`port map ( clk => clk, rst => rst,`
425			`d=> comp_dsp, q => comp_dsp1);`
426
427			`LATCH_sign_S3 : d_ff`
428			`generic map (N => 3)`
429			`port map (clk => clk, rst => rst,`
430			`d=> sign_q1, q => sign_q2);`
431
432			`LATCH_exp_S3 : d_ff`
433			`generic map (N => 9)`
434			`port map (clk => clk, rst => rst,`
435			`d=> exp_int_q1, q => exp_int_q2);`
436
437			`LATCH_sub_S4: d_ff`
438			`generic map ( N => 1)`
439			`port map ( clk => clk, rst => rst,`
440			`d=> sub_dsp1, q => sub_dsp2);`
441
442			`LATCH_comp_S4: d_ff`
443			`generic map ( N => 1)`
444			`port map ( clk => clk, rst => rst,`
445			`d=> comp_dsp1, q => comp_dsp2);`
446
447			`LATCH_sign_S4 : d_ff`
448			`generic map (N => 3)`
449			`port map (clk => clk, rst => rst,`
450			`d=> sign_q2, q => sign_q3);`
451
452			`LATCH_exp_S4 : d_ff`
453			`generic map (N => 9)`
454			`port map (clk => clk, rst => rst,`
455			`d=> exp_int_q2, q => exp_int_q3);`
456
457			`--computing the mantissa mac`
458
459			`--add_msbs_p <= (60 downto 48 => '0') & p1;`
460			`--add_lsbs_p <= p2(43 downto 0) & (16 downto 0=>'0');`
461
462			`add_msbs_p <= p1(43 downto 0) & (16 downto 0=>'0');`
463			`add_lsbs_p <= (60 downto 48 => '0') & p2(47 downto 0);`
464			`p <= add_msbs_p + add_lsbs_p;`
465
466			`--latching the result`
467
468			`LATCH_sub_S5: d_ff`
469			`generic map ( N => 1)`
470			`port map ( clk => clk, rst => rst,`
471			`d=> sub_dsp2, q => sub_dsp3);`
472
473			`LATCH_comp_S5: d_ff`
474			`generic map ( N => 1)`
475			`port map ( clk => clk, rst => rst,`
476			`d=> comp_dsp2, q => comp_dsp3);`
477
478			`LATCH_sign_S5 : d_ff`
479			`generic map (N => 3)`
480			`port map (clk => clk, rst => rst,`
481			`d=> sign_q3, q => sign_q4);`
482
483			`LATCH_exp_S5 : d_ff`
484			`generic map (N => 9)`
485			`port map (clk => clk, rst => rst,`
486			`d=> exp_int_q3, q => exp_int_q4);`
487
488			`LATCH_p_S5 : d_ff`
489			`generic map(N=>61)`
490			`port map (clk => clk, rst => rst,`
491			`d => p, q => p_q);`
492
493			`-- absolute value`
494			`sign_mantissa_add <= p_q(60);`
495
496			`mantissa_abs_d <= p_q (59 downto 0) when sign_mantissa_add = '0' else`
497			`-(p_q(59 downto 0));`
498
499			`SIGN_RESULT_COMP :`
500			`sign_comp`
501			`port map(sign_a => sign_q4(2), sign_b => sign_q4(1),`
502			`sign_c => sign_q4(0),`
503			`comp_exp => comp_dsp3(0),`
504			`eff_sub => sub_dsp3(0),`
505			`sign_add => sign_mantissa_add,`
506			`sign_res => sign_res1(0));`
507
508			`-- Fifth PIPELINE REGISTERS`
509			`-- abs value of mantissa, exp_int, sign_res`
510			`LATCH_MANTISSA_ABS_S6:`
511			`d_ff generic map (n => 60)`
512			`port map (clk => clk, rst => rst,`
513			`d => mantissa_abs_d, q=>mantissa_abs_q1);`
514
515			`LATCH_sign_res_S6 : d_ff`
516			`generic map (N => 1)`
517			`port map (clk => clk, rst => rst,`
518			`d=> sign_res1, q => sign_res2);`
519
520			`LATCH_exp_S6 : d_ff`
521			`generic map (N => 9)`
522			`port map (clk => clk, rst => rst,`
523			`d=> exp_int_q4, q => exp_int_q5);`
524
525			`--pipeline stage`
526			`ovf_mac <= mantissa_abs_q1(59) or mantissa_abs_q1(58);`
527			`LZC_COUNT : lzc_tree`
528			`generic map ( SIZE_INT => 58,`
529			`PIPELINE => 0)`
530			`port map (clk => clk, rst => rst,`
531			`a => mantissa_abs_q1(57 downto 0),`
532			`ovf => ovf_mac, lz => lzc_d);`
533			`--pipeline_registers`
534			`LATCH_MANTISSA_ABS_S7:`
535			`d_ff generic map (n => 60)`
536			`port map (clk => clk, rst => rst,`
537			`d => mantissa_abs_q1, q=>mantissa_abs_q2);`
538
539			`LATCH_sign_res_S7 : d_ff`
540			`generic map (N => 1)`
541			`port map (clk => clk, rst => rst,`
542			`d=> sign_res2, q => sign_res3);`
543
544			`LATCH_exp_S7 : d_ff`
545			`generic map (N => 9)`
546			`port map (clk => clk, rst => rst,`
547			`d=> exp_int_q5, q => exp_int_q6);`
548
549			`LATCH_lzc_S7 : d_ff`
550			`generic map (N => 6)`
551			`port map (clk => clk, rst => rst,`
552			`d=> lzc_d, q => lzc_q);`
553
554			`-- another stage`
555
556			`SHIFT_MANTISSA : shift`
557			`generic map (INPUT_SIZE => 60,`
558			`SHIFT_SIZE => 6,`
559			`OUTPUT_SIZE => 60,`
560			`DIRECTION => 1,`
561			`PIPELINE => 0)`
562			`port map (clk => clk, rst => rst,`
563			`a => mantissa_abs_q2,`
564			`shft => lzc_q,`
565			`shifted_a => mantissa_lzc_d,`
566			`arith => zero);`
567
568			`SUB_LZC_EXP :`
569			`exp_add_lzc`
570			`generic map(SIZE_EXP => 9, SIZE_LZC => 6)`
571			`port map (exp_in => exp_int_q6, lzc => lzc_q, exp_out => exp_lzc_d);`
572
573
574			`-- pipeline register 7`
575			`-- mantissa_lzc, exp_lzc, sign_res`
576			`LATCH_MANTISSA_LZC_S8:`
577			`d_ff generic map (n => 60)`
578			`port map (clk => clk, rst => rst,`
579			`d => mantissa_lzc_d, q=>mantissa_lzc_q);`
580
581			`LATCH_sign_res_S8 : d_ff`
582			`generic map (N => 1)`
583			`port map (clk => clk, rst => rst,`
584			`d=> sign_res3, q => sign_res4);`
585
586			`LATCH_exp_S8 : d_ff`
587			`generic map (N => 9)`
588			`port map (clk => clk, rst => rst,`
589			`d=> exp_lzc_d, q => exp_lzc_q);`
590
591			`--rounding`
592			`ROUND:`
593			`round_norm generic map(OPERAND_SIZE => 58,`
594			`MANTISSA_SIZE => 24,`
595			`RND_PREC => 0,`
596			`PIPELINE => 1)`
597			`port map (clk => clk, rst => rst,`
598			`mantissa_in => mantissa_lzc_q,`
599			`mantissa_out => mantissa_res_d,`
600			`ovf_norm => ovf_norm,`
601			`neg => zero,`
602			`ovf_rnd => ovf_round);`
603
604			`EXP_UPDATE:`
605			`exp_add_norm generic map (SIZE_EXP => 9, PIPELINE => 1)`
606			`port map (clk => clk, rst => rst,`
607			`exp_in => exp_lzc_q,`
608			`ovf_norm => ovf_norm,`
609			`ovf_rnd => ovf_round,`
610			`exp_out => exp_res_int);`
611
612			`--PIPELINE STAGE 6`
613			`-- sign res`
614			`LATCH_sign_res_S9 : d_ff`
615			`generic map (N => 1)`
616			`port map (clk => clk, rst => rst,`
617			`d=> sign_res4, q => sign_res5);`
618
619
620			`sign_res <= sign_res5(0);`
621			`exp_res <= exp_res_int (7 downto 0);`
622			`mantissa_res <= mantissa_res_d;`
623
624
625			`end Behavioral;`
626