Subversion Repositories xmatchpro

; Copyright 1991-2012 Mentor Graphics Corporation

;

; All Rights Reserved.

;

; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF

; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.

;

[Library]

std = $MODEL_TECH/../std

ieee = $MODEL_TECH/../ieee

vital2000 = $MODEL_TECH/../vital2000

;

; VITAL concerns:

;

; The library ieee contains (among other packages) the packages of the

; VITAL 2000 standard.  When a design uses VITAL 2000 exclusively, it should use

; the physical library ieee (recommended), or use the physical library

; vital2000, but not both.  The design can use logical library ieee and/or

; vital2000 as long as each of these maps to the same physical library, either

; ieee or vital2000.

;

; A design using the 1995 version of the VITAL packages, whether or not

; it also uses the 2000 version of the VITAL packages, must have logical library

; name ieee mapped to physical library vital1995.  (A design cannot use library

; vital1995 directly because some packages in this library use logical name ieee

; when referring to the other packages in the library.)  The design source

; should use logical name ieee when referring to any packages there except the

; VITAL 2000 packages.  Any VITAL 2000 present in the design must use logical

; name vital2000 (mapped to physical library vital2000) to refer to those

; packages.

; ieee = $MODEL_TECH/../vital1995

;

; For compatiblity with previous releases, logical library name vital2000 maps

; to library vital2000 (a different library than library ieee, containing the

; same packages).

; A design should not reference VITAL from both the ieee library and the

; vital2000 library because the vital packages are effectively different.

; A design that references both the ieee and vital2000 libraries must have

; both logical names ieee and vital2000 mapped to the same library, either of

; these:

;   $MODEL_TECH/../ieee

;   $MODEL_TECH/../vital2000

;

verilog = $MODEL_TECH/../verilog

std_developerskit = $MODEL_TECH/../std_developerskit

synopsys = $MODEL_TECH/../synopsys

modelsim_lib = $MODEL_TECH/../modelsim_lib

sv_std = $MODEL_TECH/../sv_std

mtiAvm = $MODEL_TECH/../avm

mtiOvm = $MODEL_TECH/../ovm-2.1.2

mtiUvm = $MODEL_TECH/../uvm-1.1a

mtiUPF = $MODEL_TECH/../upf_lib

mtiPA  = $MODEL_TECH/../pa_lib

floatfixlib = $MODEL_TECH/../floatfixlib

mc2_lib = $MODEL_TECH/../mc2_lib

;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release

;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release

;mvc_lib = $MODEL_TECH/../mvc_lib

work = work

xil_lib = xil_lib

xilinxcorelib = C:/Users/eejlny/Downloads/xilinxcorelib/xilinxcorelib

dzx = dzx

[vcom]

; VHDL93 variable selects language version as the default.

; Default is VHDL-2002.

; Value of 0 or 1987 for VHDL-1987.

; Value of 1 or 1993 for VHDL-1993.

; Default or value of 2 or 2002 for VHDL-2002.

; Value of 3 or 2008 for VHDL-2008

VHDL93 = 2002

; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.

; ignoreStandardRealVector = 1

; Show source line containing error. Default is off.

; Show_source = 1

; Turn off unbound-component warnings. Default is on.

; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.

; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.

; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.

; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.

; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.

; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the

; "explicit" function declaration (not the one automatically created by

; the compiler for each type declaration). Default is off.

; The .ini file has Explicit enabled so that std_logic_signed/unsigned

; will match the behavior of synthesis tools.

Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.

; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.

; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.

; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.

; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messages. Default is to show warnings.

; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.

; EmbeddedPsl = 0

; Keep silent about case statement static warnings.

; Default is to give a warning.

; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.

; Default is to give a warning.

; NoOthersStaticError = 1

; Treat as errors:

;   case statement static warnings

;   warnings caused by aggregates that are not locally static

; Overrides NoCaseStaticError, NoOthersStaticError settings.

; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.

; Default is to include debugging info.

; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.

; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:

;    -- signals used (read) by a process must be in the sensitivity list

; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,

; waits, or function/procedure/task invocations. Default is off.

; ScalarOpts = 1

; Turns on lint-style checking.

; Show_Lint = 1

; Require the user to specify a configuration for all bindings,

; and do not generate a compile time default binding for the

; component. This will result in an elaboration error of

; 'component not bound' if the user fails to do so. Avoids the rare

; issue of a false dependency upon the unused default binding.

; RequireConfigForAllDefaultBinding = 1

; Perform default binding at compile time.

; Default is to do default binding at load time.

; BindAtCompile = 1;

; Inhibit range checking on subscripts of arrays. Range checking on

; scalars defined with subtypes is inhibited by default.

; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to

; scalar objects defined with subtypes.

; NoRangeCheck = 1

; Run the 0-in compiler on the VHDL source files

; Default is off.

; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.

; Default is "".

; ZeroInOptions = ""

; Set the prefix to be honored for synthesis/coverage pragma recognition.

; Default is "".

; AddPragmaPrefix = ""

; Ignore synthesis and coverage pragmas with this prefix.

; Default is "".

; IgnorePragmaPrefix = ""

; Turn on code coverage in VHDL design units. Default is off.

; Coverage = sbceft

; Turn off code coverage in VHDL subprograms. Default is on.

; CoverSub = 0

; Automatically exclude VHDL case statement OTHERS choice branches.

; This includes OTHERS choices in selected signal assigment statements.

; Default is to not exclude.

; CoverExcludeDefault = 1

; Control compiler and VOPT optimizations that are allowed when

; code coverage is on.  Refer to the comment for this in the [vlog] area.

; CoverOpt = 3

; Turn on or off clkOpt optimization for code coverage. Default is on.

; CoverClkOpt = 1

; Turn on or off clkOpt optimization builtins for code coverage. Default is on.

; CoverClkOptBuiltins = 0

; Inform code coverage optimizations to respect VHDL 'H' and 'L'

; values on signals in conditions and expressions, and to not automatically

; convert them to '1' and '0'. Default is to not convert.

; CoverRespectHandL = 0

; Increase or decrease the maximum number of rows allowed in a FEC table, implementing

; a condition coverage or expression coverage expression, by changing FecEffort.

; Higher FecEffort leads to a longer compile time, but more expressions covered.

; This is a number from 1 to 3, with the following meanings (the default is 1):

;    3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.

;    2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.

;    1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.

; FecEffort = 2

; Enable or disable Focused Expression Coverage analysis for conditions and

; expressions. Focused Expression Coverage data is provided by default when

; expression and/or condition coverage is active.

; CoverFEC = 0

; Enable or disable UDP Coverage analysis for conditions and expressions.

; UDP Coverage data is disabled by default when expression and/or condition

; coverage is active.

; CoverUDP = 1

; Enable or disable short circuit evaluation of conditions and expressions when

; condition or expression coverage is active. Short circuit evaluation is enabled

; by default.

; CoverShortCircuit = 0

; Enable code coverage reporting of code that has been optimized away.

; The default is not to report.

; CoverReportCancelled = 1

; Use this directory for compiler temporary files instead of "work/_temp"

; CompilerTempDir = /tmp

; Set this to cause the compilers to force data to be committed to disk

; when the files are closed.

; SyncCompilerFiles = 1

; Add VHDL-AMS declarations to package STANDARD

; Default is not to add

; AmsStandard = 1

; Range and length checking will be performed on array indices and discrete

; ranges, and when violations are found within subprograms, errors will be

; reported. Default is to issue warnings for violations, because subprograms

; may not be invoked.

; NoDeferSubpgmCheck = 0

; Turn ON detection of FSMs having single bit current state variable.

; FsmSingle = 1

; Turn off reset state transitions in FSM.

; FsmResetTrans = 0

; Turn ON detection of FSM Implicit Transitions.

; FsmImplicitTrans = 1

; Controls whether or not to show immediate assertions with constant expressions

; in GUI/report/UCDB etc. By default, immediate assertions with constant

; expressions are shown in GUI/report/UCDB etc. This does not affect

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

; Controls how VHDL basic identifiers are stored with the design unit.

; Does not make the language case-sensitive, affects only how declarations

; declared with basic identifiers have their names stored and printed

; (in the GUI, examine, etc.).

; Default is to preserve the case as originally depicted in the VHDL source.

; Value of 0 indicates to change all basic identifiers to lower case.

; PreserveCase = 0

; For Configuration Declarations, controls the effect that USE clauses have

; on visibility inside the configuration items being configured.  If 1

; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,

; extend the visibility of objects made visible through USE clauses into nested

; component configurations.

; OldVHDLConfigurationVisibility = 0

; Allows VHDL configuration declarations to be in a different library from

; the corresponding configured entity. Default is to not allow this for

; stricter LRM-compliance.

; SeparateConfigLibrary = 1;

; Determine how mode OUT subprogram parameters of type array and record are treated.

; If 0 (the default), then only VHDL 2008 will do this initialization.

; If 1, always initialize the mode OUT parameter to its default value.

; If 2, do not initialize the mode OUT out parameter.

; Note that prior to release 10.1, all language versions did not initialize mode

; OUT array and record type parameters, unless overridden here via this mechanism.

; In release 10.1 and later, only files compiled with VHDL 2008 will cause this

; initialization, unless overridden here.

; InitOutCompositeParam = 0

[vlog]

; Turn off inclusion of debugging info within design units.

; Default is to include debugging info.

; NoDebug = 1

; Turn on `protect compiler directive processing.

; Default is to ignore `protect directives.

; Protect = 1

; Turn off "Loading..." messages. Default is messages on.

; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).

; Default is off.

; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case

; insensitivity for module names. Default is no conversion.

; UpCase = 1

; Activate optimizations on expressions that do not involve signals,

; waits, or function/procedure/task invocations. Default is off.

; ScalarOpts = 1

; Turns on lint-style checking.

; Show_Lint = 1

; Show source line containing error. Default is off.

; Show_source = 1

; Turn on bad option warning. Default is off.

; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).

; vlog95compat = 1

; Turn off PSL warning messages. Default is to show warnings.

; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.

; EmbeddedPsl = 0

; Set the threshold for automatically identifying sparse Verilog memories.

; A memory with depth equal to or more than the sparse memory threshold gets

; marked as sparse automatically, unless specified otherwise in source code

; or by +nosparse commandline option of vlog or vopt.

; The default is 1M.  (i.e. memories with depth equal

; to or greater than 1M are marked as sparse)

; SparseMemThreshold = 1048576

; Run the 0-in compiler on the Verilog source files

; Default is off.

; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.

; Default is "".

; ZeroInOptions = ""

; Set the prefix to be honored for synthesis and coverage pragma recognition.

; Default is "".

; AddPragmaPrefix = ""

; Ignore synthesis and coverage pragmas with this prefix.

; Default is "".

; IgnorePragmaPrefix = ""

; Set the option to treat all files specified in a vlog invocation as a

; single compilation unit. The default value is set to 0 which will treat

; each file as a separate compilation unit as specified in the P1800 draft standard.

; MultiFileCompilationUnit = 1

; Turn on code coverage in Verilog design units. Default is off.

; Coverage = sbceft

; Automatically exclude Verilog case statement default branches.

; Default is to not automatically exclude defaults.

; CoverExcludeDefault = 1

; Increase or decrease the maximum number of rows allowed in a FEC table, implementing

; a condition coverage or expression coverage expression, by changing FecEffort.

; Higher FecEffort leads to a longer compile time, but more expressions covered.

; This is a number from 1 to 3, with the following meanings (the default is 1):

;    3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.

;    2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.

;    1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.

; FecEffort = 2

; Enable or disable Focused Expression Coverage analysis for conditions and

; expressions. Focused Expression Coverage data is provided by default when

; expression and/or condition coverage is active.

; CoverFEC = 0

; Enable or disable UDP Coverage analysis for conditions and expressions.

; UDP Coverage data is disabled by default when expression and/or condition

; coverage is active.

; CoverUDP = 1

; Enable or disable short circuit evaluation of conditions and expressions when

; condition or expression coverage is active. Short circuit evaluation is enabled

; by default.

; CoverShortCircuit = 0

; Turn on code coverage in VLOG `celldefine modules, modules containing

; specify blocks, and modules included using vlog -v and -y. Default is off.

; CoverCells = 1

; Enable code coverage reporting of code that has been optimized away.

; The default is not to report.

; CoverReportCancelled = 1

; Control compiler and VOPT optimizations that are allowed when

; code coverage is on. This is a number from 0 to 5, with the following

; meanings (the default is 3):

;    5 -- All allowable optimizations are on.

;    4 -- Turn off removing unreferenced code.

;    3 -- Turn off process, always block and if statement merging.

;    2 -- Turn off expression optimization, converting primitives

;         to continuous assignments, VHDL subprogram inlining.

;         and VHDL clkOpt (converting FF's to builtins).

;    1 -- Turn off continuous assignment optimizations and clock suppression.

;    0 -- Turn off Verilog module inlining and VHDL arch inlining.

; HOWEVER, if fsm coverage is turned on, optimizations will be forced to

; level 3, with also turning off converting primitives to continuous assigns.

; CoverOpt = 3

; Specify the override for the default value of "cross_num_print_missing"

; option for the Cross in Covergroups. If not specified then LRM default

; value of 0 (zero) is used. This is a compile time option.

; SVCrossNumPrintMissingDefault = 0

; Setting following to 1 would cause creation of variables which

; would represent the value of Coverpoint expressions. This is used

; in conjunction with "SVCoverpointExprVariablePrefix" option

; in the modelsim.ini

; EnableSVCoverpointExprVariable = 0

; Specify the override for the prefix used in forming the variable names

; which represent the Coverpoint expressions. This is used in conjunction with

; "EnableSVCoverpointExprVariable" option of the modelsim.ini

; The default prefix is "expr".

; The variable name is

;    variable name => _

; SVCoverpointExprVariablePrefix = expr

; Override for the default value of the SystemVerilog covergroup,

; coverpoint, and cross option.goal (defined to be 100 in the LRM).

; NOTE: It does not override specific assignments in SystemVerilog

; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"

; in the [vsim] section can override this value.

; SVCovergroupGoalDefault = 100

; Override for the default value of the SystemVerilog covergroup,

; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)

; NOTE: It does not override specific assignments in SystemVerilog

; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"

; in the [vsim] section can override this value.

; SVCovergroupTypeGoalDefault = 100

; Specify the override for the default value of "strobe" option for the

; Covergroup Type. This is a compile time option which forces "strobe" to

; a user specified default value and supersedes SystemVerilog specified

; default value of '0'(zero). NOTE: This can be overriden by a runtime

; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.

; SVCovergroupStrobeDefault = 0

; Specify the override for the default value of "merge_instances" option for

; the Covergroup Type. This is a compile time option which forces

; "merge_instances" to a user specified default value and supersedes

; SystemVerilog specified default value of '0'(zero).

; SVCovergroupMergeInstancesDefault = 0

; Specify the override for the default value of "per_instance" option for the

; Covergroup variables. This is a compile time option which forces "per_instance"

; to a user specified default value and supersedes SystemVerilog specified

; default value of '0'(zero).

; SVCovergroupPerInstanceDefault = 0

; Specify the override for the default value of "get_inst_coverage" option for the

; Covergroup variables. This is a compile time option which forces

; "get_inst_coverage" to a user specified default value and supersedes

; SystemVerilog specified default value of '0'(zero).

; SVCovergroupGetInstCoverageDefault = 0

;

; A space separated list of resource libraries that contain precompiled

; packages.  The behavior is identical to using the "-L" switch.

;

; LibrarySearchPath =  [ ...]

LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF

; The behavior is identical to the "-mixedansiports" switch.  Default is off.

; MixedAnsiPorts = 1

; Enable SystemVerilog 3.1a $typeof() function. Default is off.

; EnableTypeOf = 1

; Only allow lower case pragmas. Default is disabled.

; AcceptLowerCasePragmaOnly = 1

; Set the maximum depth permitted for a recursive include file nesting.

; IncludeRecursionDepthMax = 5

; Turn ON detection of FSMs having single bit current state variable.

; FsmSingle = 1

; Turn off reset state transitions in FSM.

; FsmResetTrans = 0

; Turn off detections of FSMs having x-assignment.

; FsmXAssign = 0

; Turn ON detection of FSM Implicit Transitions.

; FsmImplicitTrans = 1

; List of file suffixes which will be read as SystemVerilog.  White space

; in extensions can be specified with a back-slash: "\ ".  Back-slashes

; can be specified with two consecutive back-slashes: "\\";

; SVFileExtensions = sv svp svh

; This setting is the same as the vlog -sv command line switch.

; Enables SystemVerilog features and keywords when true (1).

; When false (0), the rules of IEEE Std 1364-2001 are followed and

; SystemVerilog keywords are ignored.

; Svlog = 0

; Prints attribute placed upon SV packages during package import

; when true (1).  The attribute will be ignored when this

; entry is false (0). The attribute name is "package_load_message".

; The value of this attribute is a string literal.

; Default is true (1).

; PrintSVPackageLoadingAttribute = 1

; Do not show immediate assertions with constant expressions in

; GUI/reports/UCDB etc. By default immediate assertions with constant

; expressions are shown in GUI/reports/UCDB etc. This does not affect

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

; Controls if untyped parameters that are initialized with values greater

; than 2147483647 are mapped to generics of type INTEGER or ignored.

; If mapped to VHDL Integers, values greater than 2147483647

; are mapped to negative values.

; Default is to map these parameter to generic of type INTEGER

; ForceUnsignedToVHDLInteger = 1

; Enable AMS wreal (wired real) extensions.  Default is 0.

; WrealType = 1

; Controls SystemVerilog Language Extensions.  These options enable

; some non-LRM compliant behavior.  Valid extensions are "feci",

; "pae", "uslt" and "spsl".

; SVExtensions = uslt,spsl

[sccom]

; Enable use of SCV include files and library.  Default is off.

; UseScv = 1

; Add C++ compiler options to the sccom command line by using this variable.

; CppOptions = -g

; Use custom C++ compiler located at this path rather than the default path.

; The path should point directly at a compiler executable.

; CppPath = /usr/bin/g++

; Enable verbose messages from sccom.  Default is off.

; SccomVerbose = 1

; sccom logfile.  Default is no logfile.

; SccomLogfile = sccom.log

; Enable use of SC_MS include files and library.  Default is off.

; UseScMs = 1

[vopt]

; Turn on code coverage in vopt.  Default is off.

; Coverage = sbceft

; Control compiler optimizations that are allowed when

; code coverage is on.  Refer to the comment for this in the [vlog] area.

; CoverOpt = 3

; Increase or decrease the maximum number of rows allowed in a FEC table, implementing

; a condition coverage or expression coverage expression, by changing FecEffort.

; Higher FecEffort leads to a longer compile time, but more expressions covered.

; This is a number from 1 to 3, with the following meanings (the default is 1):

;    3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.

;    2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.

;    1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.

; FecEffort = 2

; Enable code coverage reporting of code that has been optimized away.

; The default is not to report.

; CoverReportCancelled = 1

; Do not show immediate assertions with constant expressions in

; GUI/reports/UCDB etc. By default immediate assertions with constant

; expressions are shown in GUI/reports/UCDB etc. This does not affect

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

; Set the maximum number of iterations permitted for a generate loop.

; Restricting this permits the implementation to recognize infinite

; generate loops.

; GenerateLoopIterationMax = 100000

; Set the maximum depth permitted for a recursive generate instantiation.

; Restricting this permits the implementation to recognize infinite

; recursions.

; GenerateRecursionDepthMax = 200

; Set the number of processes created during the code generation phase.

; By default a heuristic is used to set this value.  This may be set to 0

; to disable this feature completely.

; ParallelJobs = 0

; Controls SystemVerilog Language Extensions.  These options enable

; some non-LRM compliant behavior.  Valid extensions are "feci",

; "pae", "uslt" and "spsl".

; SVExtensions = uslt,spsl

[vsim]

; vopt flow

; Set to turn on automatic optimization of a design.

; Default is on

VoptFlow = 1

; Simulator resolution

; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.

Resolution = ns

; Disable certain code coverage exclusions automatically.

; Assertions and FSM are exluded from the code coverage by default

; Set AutoExclusionsDisable = fsm to enable code coverage for fsm

; Set AutoExclusionsDisable = assertions to enable code coverage for assertions

; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions

; Or specify comma or space separated list

;AutoExclusionsDisable = fsm,assertions

; User time unit for run commands

; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the

; unit specified for Resolution. For example, if Resolution is 100ps,

; then UserTimeUnit defaults to ps.

; Should generally be set to default.

UserTimeUnit = default

; Default run length

RunLength = 100 ns

; Maximum iterations that can be run without advancing simulation time

IterationLimit = 5000

; Control PSL and Verilog Assume directives during simulation

; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts

; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts

; SimulateAssumeDirectives = 1

; Control the simulation of PSL and SVA

; These switches can be overridden by the vsim command line switches:

;    -psl, -nopsl, -sva, -nosva.

; Set SimulatePSL = 0 to disable PSL simulation

; Set SimulatePSL = 1 to enable PSL simulation (default)

; SimulatePSL = 1

; Set SimulateSVA = 0 to disable SVA simulation

; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)

; SimulateSVA = 1

; Control SVA and VHDL immediate assertion directives during simulation

; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts

; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts

; SimulateImmedAsserts = 1

; Directives to license manager can be set either as single value or as

; space separated multi-values:

; vhdl          Immediately reserve a VHDL license

; vlog          Immediately reserve a Verilog license

; plus          Immediately reserve a VHDL and Verilog license

; noqueue       Do not wait in the license queue when a license is not available

; viewsim       Try for viewer license but accept simulator license(s) instead

;               of queuing for viewer license (PE ONLY)

; noviewer      Disable checkout of msimviewer and vsim-viewer license

;               features (PE ONLY)

; noslvhdl      Disable checkout of qhsimvh and vsim license features

; noslvlog      Disable checkout of qhsimvl and vsimvlog license features

; nomix         Disable checkout of msimhdlmix and hdlmix license features

; nolnl         Disable checkout of msimhdlsim and hdlsim license features

; mixedonly     Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license

;               features

; lnlonly       Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,

;               hdlmix license features

; Single value:

; License = plus

; Multi-value:

; License = noqueue plus

; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion

; which will cause a running simulation to stop.

; VHDL assertions and SystemVerilog immediate assertions that occur with the

; given severity or higher will cause a running simulation to stop.

; This value is ignored during elaboration.

; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal

BreakOnAssertion = 3

; The class debug feature enables more visibility and tracking of class instances

; during simulation.  By default this feature is 0 (disabled).  To enable this

; feature set ClassDebug to 1.

; ClassDebug = 1

; Message Format conversion specifications:

; %S - Severity Level of message/assertion

; %R - Text of message

; %T - Time of message

; %D - Delta value (iteration number) of Time

; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected

; %i - Instance/Region/Signal pathname with Process name (if available)

; %I - shorthand for one of these:

;      "  %K: %i"

;      "  %K: %i File: %F" (when path is not Process or Signal)

;      except that the %i in this case does not report the Process name

; %O - Process name

; %P - Instance/Region path without leaf process

; %F - File name

; %L - Line number; if assertion message, then line number of assertion or, if

;      assertion is in a subprogram, line from which the call is made

; %u - Design unit name in form library.primary

; %U - Design unit name in form library.primary(secondary)

; %% - The '%' character itself

;

; If specific format for Severity Level is defined, use that format.

; Else, for a message that occurs during elaboration:

;   -- Failure/Fatal message in VHDL region that is not a Process, and in

;      certain non-VHDL regions, uses MessageFormatBreakLine;

;   -- Failure/Fatal message otherwise uses MessageFormatBreak;

;   -- Note/Warning/Error message uses MessageFormat.

; Else, for a message that occurs during runtime and triggers a breakpoint because

; of the BreakOnAssertion setting:

;   -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;

;   -- otherwise uses MessageFormatBreak.

; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.

;

; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"

; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; Error File - alternate file for storing error messages

; ErrorFile = error.log

; Simulation Breakpoint messages

; This flag controls the display of function names when reporting the location

; where the simulator stops because of a breakpoint or fatal error.

; Example with function name:    # Break in Process ctr at counter.vhd line 44

; Example without function name: # Break at counter.vhd line 44

; Default value is 1.

ShowFunctions = 1

; Default radix for all windows and commands.

; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned

; Flags may be one of: enumnumeric, showbase

DefaultRadix = symbolic

;DefaultRadixFlags = showbase

; VSIM Startup command

; Startup = do startup.do

; VSIM Shutdown file

; Filename to save u/i formats and configurations.

; ShutdownFile = restart.do

; To explicitly disable auto save:

; ShutdownFile = --disable-auto-save

; File for saving command transcript

TranscriptFile = transcript

; File for saving command history

; CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described

; in VHDL or Verilog format.

; For VHDL, PathSeparator = /

; For Verilog, PathSeparator = .

; Must not be the same character as DatasetSeparator.

PathSeparator = /

; Specify the dataset separator for fully rooted contexts.

; The default is ':'. For example: sim:/top

; Must not be the same character as PathSeparator.

DatasetSeparator = :

; Specify a unique path separator for the Signal Spy set of functions.

; The default will be to use the PathSeparator variable.

; Must not be the same character as DatasetSeparator.

; SignalSpyPathSeparator = /

; Used to control parsing of HDL identifiers input to the tool.

; This includes CLI commands, vsim/vopt/vlog/vcom options,

; string arguments to FLI/VPI/DPI calls, etc.

; If set to 1, accept either Verilog escaped Id syntax or

; VHDL extended id syntax, regardless of source language.

; If set to 0, the syntax of the source language must be used.

; Each identifier in a hierarchical name may need different syntax,

; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or

;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"

; GenerousIdentifierParsing = 1

; Disable VHDL assertion messages

; IgnoreNote = 1

; IgnoreWarning = 1

; IgnoreError = 1

; IgnoreFailure = 1

; Disable SystemVerilog assertion messages

; IgnoreSVAInfo = 1

; IgnoreSVAWarning = 1

; IgnoreSVAError = 1

; IgnoreSVAFatal = 1

; Do not print any additional information from Severity System tasks.

; Only the message provided by the user is printed along with severity

; information.

; SVAPrintOnlyUserMessage = 1;

; Default force kind. May be freeze, drive, deposit, or default

; or in other terms, fixed, wired, or charged.

; A value of "default" will use the signal kind to determine the

; force kind, drive for resolved signals, freeze for unresolved signals

; DefaultForceKind = freeze

; Control the iteration of events when a VHDL signal is forced to a value

; This flag can be set to honour the signal update event in next iteration,

; the default is to update and propagate in the same iteration.

; ForceSigNextIter = 1

; If zero, open files when elaborated; otherwise, open files on

; first read or write.  Default is 0.

; DelayFileOpen = 1

; Control VHDL files opened for write.

;   0 = Buffered, 1 = Unbuffered

UnbufferedOutput = 0

; Control the number of VHDL files open concurrently.

; This number should always be less than the current ulimit

; setting for max file descriptors.

;   0 = unlimited

ConcurrentFileLimit = 40

; Control the number of hierarchical regions displayed as

; part of a signal name shown in the Wave window.

; A value of zero tells VSIM to display the full name.

; The default is 0.

; WaveSignalNameWidth = 0

; Turn off warnings when changing VHDL constants and generics

; Default is 1 to generate warning messages

; WarnConstantChange = 0

; Turn off warnings from accelerated versions of the std_logic_arith,

; std_logic_unsigned, and std_logic_signed packages.

; StdArithNoWarnings = 1

; Turn off warnings from accelerated versions of the IEEE numeric_std

; and numeric_bit packages.

; NumericStdNoWarnings = 1

; Use old-style (pre-6.6) VHDL FOR generate statement iteration names

; in the design hierarchy.

; This style is controlled by the value of the GenerateFormat

; value described next.  Default is to use new-style names, which

; comprise the generate statement label, '(', the value of the generate

; parameter, and a closing ')'.

; Uncomment this to use old-style names.

; OldVhdlForGenNames = 1

; Control the format of the old-style VHDL FOR generate statement region

; name for each iteration.  Do not quote it.

; The format string here must contain the conversion codes %s and %d,

; in that order, and no other conversion codes.  The %s represents

; the generate statement label; the %d represents the generate parameter value

; at a particular iteration (this is the position number if the generate parameter

; is of an enumeration type).  Embedded whitespace is allowed (but discouraged);

; leading and trailing whitespace is ignored.

; Application of the format must result in a unique region name over all

; loop iterations for a particular immediately enclosing scope so that name

; lookup can function properly.  The default is %s__%d.

; GenerateFormat = %s__%d

; Enable changes in VHDL elaboration to allow for Variable Logging

; This trades off simulation performance for the ability to log variables

; efficiently.  By default this is disable for maximum simulation performance

; VhdlVariableLogging = 1

; Specify whether checkpoint files should be compressed.

; The default is 1 (compressed).

; CheckpointCompressMode = 0

; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.

; Use custom gcc compiler located at this path rather than the default path.

; The path should point directly at a compiler executable.

; DpiCppPath = /bin/gcc

; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.

; The term "out-of-the-blue" refers to SystemVerilog export function calls

; made from C functions that don't have the proper context setup

; (as is the case when running under "DPI-C" import functions).

; When this is enabled, one can call a DPI export function

; (but not task) from any C code.

; the setting of this variable can be one of the following values:

; 0 : dpioutoftheblue call is disabled (default)

; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.

; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.

; DpiOutOfTheBlue = 1

; Specify whether continuous assignments are run before other normal priority

; processes scheduled in the same iteration. This event ordering minimizes race

; differences between optimized and non-optimized designs, and is the default

; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set

; ImmediateContinuousAssign to 0.

; The default is 1 (enabled).

; ImmediateContinuousAssign = 0

; List of dynamically loaded objects for Verilog PLI applications

; Veriuser = veriuser.sl

; Which default VPI object model should the tool conform to?

; The 1364 modes are Verilog-only, for backwards compatibility with older

; libraries, and SystemVerilog objects are not available in these modes.

;

; In the absence of a user-specified default, the tool default is the