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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [DECODING_BUFFER_32_64_2.vhd] - Blame information for rev 8

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1 8 eejlny
--This library is free software; you can redistribute it and/or
2
--modify it under the terms of the GNU Lesser General Public
3
--License as published by the Free Software Foundation; either
4
--version 2.1 of the License, or (at your option) any later version.
5
 
6
--This library is distributed in the hope that it will be useful,
7
--but WITHOUT ANY WARRANTY; without even the implied warranty of
8
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
9
--Lesser General Public License for more details.
10
 
11
--You should have received a copy of the GNU Lesser General Public
12
--License along with this library; if not, write to the Free Software
13
--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
14
 
15
-- e_mail : j.l.nunez-yanez@byacom.co.uk
16
 
17
---------------------------------------------
18
--  ENTITY       = DECODING_BUFFER_32_64   --
19
--  version      = 1.0                     --
20
--  last update  = 16/06/00                --
21
--  author       = Jose Nunez              --
22
---------------------------------------------
23
 
24
 
25
-- FUNCTION
26
-- Adapter that changes the 32 bit parallel interface to a 64 bit parallel for uncompressing
27
 
28
--  PIN LIST
29
 
30
--  START = activate the buffer
31
--  FINISHED = the block has been process. empty buffer
32
--  OVERFLOW = 64 bit of compressed data available.
33
--  DATA_IN_64  = input data from the 64 bit out register in X-MatchPRO
34
--  THRESHOLD_LEVEL = input treshold to start outputting data. Latency control.
35
--  BUS_ACKNOWLEDGE = The 32 bit wide output bus is available.
36
--  DATA_OUT_32  = output data to the 32 bit wide output bus
37
--  OVERFLOW_DETECTED = output to the control unit buffer overflow. Stop inputting data
38
--  UNDERFLOW_DETECTED = output to the control unit buffer overflow. Stop outputting data. The bus is free.
39
--  BUS_REQUEST = output requesting bus to output compressed data
40
--  CLEAR    = asynchronous clear
41
--  CLK      = master clock
42
 
43
 
44
library ieee;
45
use ieee.std_logic_1164.all;
46
use IEEE.std_logic_arith.all;
47
library xil_lib;
48
use xil_lib.xil_comp.all;
49
use work.tech_package.all;
50
 
51
 
52
entity DECODING_BUFFER_32_64_2 is
53
port
54
(
55
  FORCE_STOP : in bit;
56
        START_D : in bit;
57
        START_C : in bit;
58
        FINISHED_D : in bit;
59
        FINISHED_C : in bit;
60
        UNDERFLOW : in bit;
61
        DATA_IN_32 : in bit_vector(31 downto 0);
62
        THRESHOLD_LEVEL : in bit_vector(9 downto 0);
63
        BUS_ACKNOWLEDGE : in bit;
64
        C_DATA_VALID : in bit;
65
   WAITN : in bit;
66
        CLEAR : in bit ;
67
        CLK : in bit ;
68
        DATA_OUT_64: out bit_vector(63 downto 0);
69
        UNDERFLOW_DETECTED : out bit;
70
        START_ENGINE : out bit; -- to start the decompression engine
71
        FINISH : out bit;
72
  OVERFLOW_CONTROL : out bit;
73
        BUS_REQUEST : out bit
74
);
75
 
76
 
77
end DECODING_BUFFER_32_64_2;
78
 
79
 
80
architecture STRUCTURAL of DECODING_BUFFER_32_64_2 is
81
 
82
-- xilinx memory
83
 
84
component DP_RAM_XILINX_512
85
        port (
86
        addra: IN std_logic_VECTOR(8 downto 0);
87
        clka: IN std_logic;
88
        addrb: IN std_logic_VECTOR(8 downto 0);
89
        clkb: IN std_logic;
90
        dina: IN std_logic_VECTOR(31 downto 0);
91
        wea: IN std_logic;
92
        enb: IN std_logic;
93
        doutb: OUT std_logic_VECTOR(31 downto 0));
94
end component;
95
 
96
-- Synplicity black box declaration
97
--attribute black_box : boolean;
98
--attribute black_box of DP_RAM_XILINX: component is true;
99
 
100
 
101
-- Actel memory
102
 
103
-- component MY_MEMORY
104
 
105
--   port(DO : out std_logic_vector (31 downto 0);
106
--      RCLOCK : in std_logic;
107
--      WCLOCK : in std_logic;
108
--      DI : in std_logic_vector (31 downto 0);
109
--      WRB : in std_logic;
110
--      RDB : in std_logic;
111
--      WADDR : in std_logic_vector (7 downto 0);
112
--      RADDR : in std_logic_vector (7 downto 0));
113
 
114
--end component;
115
 
116
 
117
--component syn_dpram_256x32_rawr
118
--port (
119
--              Data : in std_logic_vector(31 downto 0);
120
--              RdAddress : in std_logic_vector(7 downto 0);
121
--              WrAddress : in std_logic_vector(7 downto 0);
122
--              RdEn : in std_logic;
123
--              WrEn : in std_logic;
124
--              Q : out std_logic_vector(31 downto 0);
125
--              RdClock : in std_logic;
126
--              RdClken : in std_logic;
127
--              WrClock : in std_logic;
128
--              WrClken : in std_logic
129
--           );
130
--end component;
131
 
132
 
133
 
134
--component LPM_RAM_DP
135
--      generic (LPM_WIDTH    : positive ;
136
--               LPM_WIDTHAD  : positive;
137
--               LPM_NUMWORDS : positive;
138
--               LPM_INDATA   : string;
139
--               LPM_RDADDRESS_CONTROL : string;
140
--               LPM_WRADDRESS_CONTROL : string;
141
--               LPM_OUTDATA  : string;
142
--               LPM_TYPE     : string;
143
--               LPM_FILE     : string;
144
--             LPM_HINT     : string);
145
--      port (RDCLOCK : in std_logic;
146
--            RDCLKEN : in std_logic;
147
--            RDADDRESS : in std_logic_vector(8 downto 0);
148
--            RDEN : in std_logic;
149
--            DATA : in std_logic_vector(31 downto 0);
150
--            WRADDRESS : in std_logic_vector(8 downto 0);
151
--            WREN : in std_logic;
152
--            WRCLOCK : in std_logic;
153
--            WRCLKEN : in std_logic;
154
--            Q : out std_logic_vector(31 downto 0));
155
-- end component;
156
 
157
 
158
-- TSMC DPRAM
159
 
160
  component ra2sh_512W_32B_16MX_offWRMSK_8WRGRAN
161
 
162
  port (
163
        CLKA: in std_logic;
164
        CENA: in std_logic;
165
        WENA: in std_logic;
166
        AA: in std_logic_vector(8 downto 0);
167
        DA: in std_logic_vector(31 downto 0);
168
        QA: out std_logic_vector(31 downto 0);
169
        CLKB: in std_logic;
170
        CENB: in std_logic;
171
        WENB: in std_logic;
172
        AB: in std_logic_vector(8 downto 0);
173
        DB: in std_logic_vector(31 downto 0);
174
        QB: out std_logic_vector(31 downto 0)
175
   );
176
 
177
end component;
178
 
179
--attribute noopt: boolean;
180
--attribute noopt of LPM_RAM_DP: component is true;
181
 
182
component DECODING_BUFFER_CU_2
183
 
184
port (
185
    FORCE_STOP : in bit;
186
          START_D : in bit;
187
          START_C : in bit;
188
          FINISHED_D : in bit;
189
          FINISHED_C : in bit;
190
          UNDERFLOW : in bit;
191
          BUS_ACKNOWLEDGE : in bit;
192
                WAITN : in bit;
193
          C_DATA_VALID : in bit;
194
          THRESHOLD_LEVEL : in bit_vector(9 downto 0);
195
          DECODING_READ_ADDRESS : in bit_vector(9 downto 0);
196
          DECODING_WRITE_ADDRESS : in bit_vector(9 downto 0);
197
          CLK : in bit;
198
          CLEAR : in bit;
199
          BUS_REQUEST : out bit;
200
          DECODING_UNDERFLOW : out bit;
201
          ENABLE_WRITE : out bit;
202
          FINISH: out bit;
203
      CLEAR_COUNTERS : out bit;
204
    OVERFLOW_CONTROL : out bit;
205
          ENABLE_READ : out bit
206
         );
207
end component;
208
 
209
 
210
 
211
component BUFFER_COUNTER_READ_9BITS
212
 
213
port (ENABLE : in bit;
214
          CLEAR : in bit;
215
          CLEAR_COUNTERS : in bit;
216
          CLK : in bit;
217
          COUNT : out bit_vector(9 downto 0)
218
     );
219
 
220
end component;
221
 
222
component BUFFER_COUNTER_WRITE_9BITS
223
 
224
port (ENABLE : in bit;
225
                SHORT : in bit; -- only write 32 bits
226
          CLEAR : in bit;
227
          CLEAR_COUNTERS : in bit;
228
          CLK : in bit;
229
          COUNT : out bit_vector(9 downto 0)
230
     );
231
end component;
232
 
233
 
234
 
235
 
236
-- 1 bit for the 64-to-32 multiplexor
237
 
238
signal DECODING_READ_ADDRESS : bit_vector(9 downto 0);
239
signal DECODING_WRITE_ADDRESS : bit_vector(9 downto 0);
240
signal DECODING_UNDERFLOW : bit;
241
signal ENABLE_READ : bit;
242
signal DATA_OUT_AUX : std_logic_vector(63 downto 0);
243
signal READ_CLK : bit;
244
signal WRITE_CLK : bit;
245
signal WRITE_CLK_ENABLE : bit;
246
signal READ_CLK_ENABLE : bit;
247
signal ENABLE_READ_INT : bit;
248
signal ENABLE_WRITE_INT : bit;
249
signal ENABLE_WRITE_MSB : bit;
250
signal ENABLE_WRITE_LSB : bit;
251
signal ENABLE_WRITE : bit;
252
signal CLEAR_COUNTERS : bit;
253
 
254
signal DATA_MSB : std_logic_vector(31 downto 0);
255
signal RDADDRESS_MSB : std_logic_vector(8 downto 0);
256
signal WRADDRESS_MSB : std_logic_vector(8 downto 0);
257
signal RDEN_MSB : std_logic;
258
signal WREN_MSB : std_logic;
259
signal RDCLOCK_MSB : std_logic;
260
signal RDCLKEN_MSB : std_logic;
261
signal WRCLOCK_MSB : std_logic;
262
signal WRCLKEN_MSB : std_logic;
263
 
264
signal DATA_LSB : std_logic_vector(31 downto 0);
265
signal RDADDRESS_LSB : std_logic_vector(8 downto 0);
266
signal WRADDRESS_LSB : std_logic_vector(8 downto 0);
267
signal RDEN_LSB : std_logic;
268
signal WREN_LSB : std_logic;
269
signal RDCLOCK_LSB : std_logic;
270
signal RDCLKEN_LSB : std_logic;
271
signal WRCLOCK_LSB : std_logic;
272
signal WRCLKEN_LSB : std_logic;
273
 
274
signal SHORT : bit;
275
 
276
 
277
 
278
signal tsmc_lsb_cena_n , tsmc_lsb_cenb_n : std_logic;
279
signal tsmc_lsb_wena_n , tsmc_lsb_wenb_n : std_logic;
280
signal tsmc_msb_cena_n , tsmc_msb_cenb_n : std_logic;
281
signal tsmc_msb_wena_n , tsmc_msb_wenb_n : std_logic;
282
 
283
 
284
 
285
 
286
 
287
begin
288
 
289
 
290
 
291
 
292
CONTROL_UNIT : DECODING_BUFFER_CU_2
293
port map(
294
    FORCE_STOP => FORCE_STOP,
295
          START_D => START_D,
296
          START_C => START_C,
297
          FINISHED_D => FINISHED_D,
298
          FINISHED_C => FINISHED_C,
299
          UNDERFLOW => UNDERFLOW, -- the engine is requesting data
300
          BUS_ACKNOWLEDGE => BUS_ACKNOWLEDGE,
301
                WAITN => WAITN,
302
          C_DATA_VALID => C_DATA_VALID,
303
          THRESHOLD_LEVEL => THRESHOLD_LEVEL,
304
          DECODING_READ_ADDRESS => DECODING_READ_ADDRESS,
305
          DECODING_WRITE_ADDRESS => DECODING_WRITE_ADDRESS,
306
          CLK => CLK,
307
          CLEAR => CLEAR,
308
          DECODING_UNDERFLOW=> DECODING_UNDERFLOW,
309
          ENABLE_WRITE => ENABLE_WRITE_INT,
310
          FINISH => FINISH,
311
          ENABLE_READ => ENABLE_READ_INT,
312
          CLEAR_COUNTERS => CLEAR_COUNTERS,
313
    OVERFLOW_CONTROL => OVERFLOW_CONTROL,
314
          BUS_REQUEST => BUS_REQUEST
315
         );
316
 
317
UNDERFLOW_DETECTED <= DECODING_UNDERFLOW;
318
 
319
READ_COUNTER : BUFFER_COUNTER_WRITE_9BITS
320
port map(ENABLE => ENABLE_READ,
321
                SHORT => SHORT,
322
                CLEAR => CLEAR,
323
          CLEAR_COUNTERS => CLEAR_COUNTERS,
324
          CLK => CLK,
325
          COUNT => DECODING_READ_ADDRESS
326
     );
327
 
328
SHORT <= '1';
329
 
330
 
331
WRITE_COUNTER : BUFFER_COUNTER_READ_9BITS
332
port map(ENABLE => ENABLE_WRITE,
333
          CLEAR =>CLEAR,
334
      CLEAR_COUNTERS => CLEAR_COUNTERS,
335
          CLK => CLK,
336
          COUNT => DECODING_WRITE_ADDRESS
337
     );
338
 
339
-- xilinx memory
340
 
341
RAM_MSB : DP_RAM_XILINX_512
342
                port map (
343
                        addra => WRADDRESS_MSB,
344
                        clka =>  WRCLOCK_MSB,
345
                        addrb => RDADDRESS_MSB,
346
                        clkb => RDCLOCK_MSB,
347
                        dina => DATA_MSB,
348
                        wea => WREN_MSB,
349
                        enb =>  RDEN_MSB,
350
                        doutb =>  DATA_OUT_AUX(63 downto 32));
351
 
352
 
353
-- Actel memory
354
 
355
--RAM_MSB : MY_MEMORY
356
--port map(DO => DATA_OUT_AUX(63 downto 32),
357
--      RCLOCK =>RDCLOCK_MSB,
358
--      WCLOCK =>WRCLOCK_MSB,
359
--      DI => DATA_MSB,
360
--      WRB => WREN_MSB,
361
--      RDB =>RDEN_MSB,
362
--      WADDR => WRADDRESS_MSB,
363
--      RADDR => RDADDRESS_MSB
364
--);
365
 
366
 
367
-- Altera memory
368
 
369
-- Altera memory
370
 
371
 
372
--ALT_RAM_MSB :
373
--
374
--if (not TSMC013) generate
375
--
376
--
377
--RAM_MSB : LPM_RAM_DP
378
--generic map(LPM_WIDTH => 32,
379
--         LPM_WIDTHAD  => 9,
380
--         LPM_NUMWORDS => 512,
381
--               LPM_INDATA => "REGISTERED",
382
--         LPM_OUTDATA  =>  "UNREGISTERED",
383
--               LPM_RDADDRESS_CONTROL => "REGISTERED",
384
--               LPM_WRADDRESS_CONTROL => "REGISTERED",
385
--               LPM_FILE  => "UNUSED",
386
--               LPM_TYPE  => "LPM_RAM_DP",
387
--               LPM_HINT => "UNUSED")         
388
--port map(
389
--             DATA=>DATA_MSB,
390
--             RDADDRESS=>RDADDRESS_MSB ,
391
--             WRADDRESS=>WRADDRESS_MSB ,
392
--             RDEN=>RDEN_MSB ,
393
--             WREN=>WREN_MSB ,
394
--             Q=> DATA_OUT_AUX(63 downto 32),
395
--             RDCLOCK=> RDCLOCK_MSB,
396
--             RDCLKEN=> RDCLKEN_MSB ,
397
--             WRCLOCK=> WRCLOCK_MSB,
398
--             WRCLKEN=> WRCLKEN_MSB
399
--);
400
--end generate;
401
 
402
--TSMC013_RAM_MSB :
403
--
404
--  if (TSMC013) generate
405
--    TMSC_RAM : ra2sh_512W_32B_16MX_offWRMSK_8WRGRAN port map
406
--      (
407
--        clka        =>      RDCLOCK_MSB,
408
--        cena        =>      tsmc_msb_cena_n ,
409
--        wena        =>      tsmc_msb_wena_n,
410
--        aa          =>      RDADDRESS_MSB,
411
--        da          =>      DATA_MSB,
412
--        qa          =>      DATA_OUT_AUX(63 downto 32),
413
--        clkb        =>      WRCLOCK_MSB,
414
--        cenb        =>      tsmc_msb_cenb_n,
415
--        wenb        =>      tsmc_msb_wenb_n,
416
--        ab          =>      WRADDRESS_MSB,
417
--        db          =>      DATA_MSB,
418
--        qb          =>      OPEN
419
--      ) ;      
420
--
421
--  end generate;
422
 
423
 
424
tsmc_msb_cenb_n <= not (WRCLKEN_MSB);
425
tsmc_msb_cena_n <= not (RDCLKEN_MSB);
426
tsmc_msb_wena_n <='1';
427
 
428
--    not (RDEN_SB); Always in read-mode; read-enable used to
429
 
430
--    power-up ram
431
 
432
tsmc_msb_wenb_n <= not (WREN_MSB);
433
 
434
 
435
DATA_MSB<=To_X01Z(DATA_IN_32) after 5 ns;
436
RDADDRESS_MSB<= To_X01Z(DECODING_READ_ADDRESS(9 downto 1)) after 5 ns;
437
WRADDRESS_MSB<= To_X01Z(DECODING_WRITE_ADDRESS(9 downto 1)) after 5 ns;
438
RDEN_MSB<= To_X01Z(ENABLE_READ) after 5 ns;
439
WREN_MSB<= To_X01Z(ENABLE_WRITE_MSB) after 5 ns;
440
RDCLOCK_MSB<= To_X01Z(READ_CLK);
441
RDCLKEN_MSB<= To_X01Z(READ_CLK_ENABLE) after 5 ns;
442
WRCLOCK_MSB<= To_X01Z(WRITE_CLK);
443
WRCLKEN_MSB<= To_X01Z(WRITE_CLK_ENABLE) after 5 ns;
444
 
445
 
446
--RAM_MSB : syn_dpram_256x32_rawr
447
--port map(
448
--              DATA=>To_X01Z(DATA_IN_32),
449
--              RDADDRESS=> To_X01Z(DECODING_READ_ADDRESS),
450
--              WRADDRESS=> To_X01Z(DECODING_WRITE_ADDRESS),
451
--              RDEN=> To_X01Z(ENABLE_READ),
452
--              WREN=> To_X01Z(ENABLE_WRITE_MSB),
453
--              Q=> DATA_OUT_AUX(63 downto 32),
454
--              RDCLOCK=> To_X01Z(READ_CLK),
455
--              RDCLKEN=> To_X01Z(READ_CLK_ENABLE),
456
--              WRCLOCK=> To_X01Z(WRITE_CLK),
457
--              WRCLKEN=> To_X01Z(WRITE_CLK_ENABLE)
458
--);
459
 
460
 
461
RAM_LSB : DP_RAM_XILINX_512
462
                port map (
463
                        addra => WRADDRESS_LSB,
464
                        clka =>  WRCLOCK_LSB,
465
                        addrb => RDADDRESS_LSB,
466
                        clkb => RDCLOCK_LSB,
467
                        dina => DATA_LSB,
468
                        wea => WREN_LSB,
469
                        enb =>  RDEN_LSB,
470
                        doutb =>  DATA_OUT_AUX(31 downto 0));
471
 
472
 
473
 
474
-- Actel memory
475
 
476
--RAM_LSB : MY_MEMORY
477
--port map(DO => DATA_OUT_AUX(31 downto 0),
478
--      RCLOCK =>RDCLOCK_LSB,
479
--      WCLOCK =>WRCLOCK_LSB,
480
--      DI => DATA_LSB,
481
--      WRB => WREN_LSB,
482
--      RDB =>RDEN_LSB,
483
--      WADDR => WRADDRESS_LSB,
484
--      RADDR => RDADDRESS_LSB
485
--);
486
 
487
-- Altera memory
488
 
489
--ALT_RAM_LSB :
490
--
491
--if (not TSMC013) generate
492
--
493
--RAM_LSB : LPM_RAM_DP
494
--generic map(LPM_WIDTH => 32,
495
--         LPM_WIDTHAD  => 9,
496
--         LPM_NUMWORDS => 512,
497
--               LPM_INDATA => "REGISTERED",
498
--         LPM_OUTDATA  =>  "UNREGISTERED",
499
--               LPM_RDADDRESS_CONTROL => "REGISTERED",
500
--               LPM_WRADDRESS_CONTROL => "REGISTERED",
501
--               LPM_FILE  => "UNUSED",
502
--               LPM_TYPE  => "LPM_RAM_DP",
503
--               LPM_HINT => "UNUSED")    
504
-- port map(
505
--             DATA=> DATA_LSB,
506
--             RDADDRESS=> RDADDRESS_LSB,
507
--             WRADDRESS=> WRADDRESS_LSB,
508
--             RDEN=> RDEN_LSB,
509
--             WREN=> WREN_LSB,
510
--             Q=> DATA_OUT_AUX(31 downto 0),
511
--             RDCLOCK=> RDCLOCK_LSB,
512
--             RDCLKEN=> RDCLKEN_LSB,
513
--             WRCLOCK=> WRCLOCK_LSB,
514
--             WRCLKEN=> WRCLKEN_LSB
515
--);
516
--
517
--end generate;
518
 
519
-- Port 1 = R
520
 
521
-- Port 2 = R/W
522
 
523
--TSMC013_RAM_LSB :
524
--
525
--  if (TSMC013) generate
526
--  TMSC_RAM : ra2sh_512W_32B_16MX_offWRMSK_8WRGRAN port map
527
--      (
528
--        clka        =>      RDCLOCK_LSB,
529
--        cena        =>      tsmc_lsb_cena_n ,
530
--        wena        =>      tsmc_lsb_wena_n,
531
--        aa          =>      RDADDRESS_LSB,
532
--        da          =>      DATA_LSB,
533
--        qa          =>      DATA_OUT_AUX(31 downto 0),
534
--        clkb        =>      WRCLOCK_LSB,
535
--        cenb        =>      tsmc_lsb_cenb_n,
536
--        wenb        =>      tsmc_lsb_wenb_n,
537
--        ab          =>      WRADDRESS_LSB,
538
--        db          =>      DATA_LSB,
539
--        qb          =>      OPEN
540
--      ) ;      
541
--end generate;
542
 
543
 
544
tsmc_lsb_cenb_n <= not (WRCLKEN_LSB);
545
tsmc_lsb_cena_n <= not (RDCLKEN_LSB);
546
tsmc_lsb_wena_n <='1';
547
 
548
--    not (RDEN_SB); Always in read-mode; read-enable used to
549
 
550
--    power-up ram
551
 
552
tsmc_lsb_wenb_n <= not (WREN_LSB);
553
 
554
 
555
DATA_LSB<=To_X01Z(DATA_IN_32) after 5 ns;
556
RDADDRESS_LSB<= To_X01Z(DECODING_READ_ADDRESS(9 downto 1)) after 5 ns;
557
WRADDRESS_LSB<= To_X01Z(DECODING_WRITE_ADDRESS(9 downto 1)) after 5 ns;
558
RDEN_LSB<= To_X01Z(ENABLE_READ) after 5 ns;
559
WREN_LSB<= To_X01Z(ENABLE_WRITE_LSB) after 5 ns;
560
RDCLOCK_LSB<= To_X01Z(READ_CLK);
561
RDCLKEN_LSB<= To_X01Z(READ_CLK_ENABLE) after 5 ns;
562
WRCLOCK_LSB<= To_X01Z(WRITE_CLK);
563
WRCLKEN_LSB<= To_X01Z(WRITE_CLK_ENABLE) after 5 ns;
564
 
565
--RAM_LSB : syn_dpram_256x32_rawr
566
--port map(
567
--              DATA=>To_X01Z(DATA_IN_32),
568
--              RDADDRESS=> To_X01Z(DECODING_READ_ADDRESS),
569
--              WRADDRESS=> To_X01Z(DECODING_WRITE_ADDRESS),
570
--              RDEN=> To_X01Z(ENABLE_READ),
571
--              WREN=> To_X01Z(ENABLE_WRITE_LSB),
572
--              Q=> DATA_OUT_AUX(31 downto 0),
573
--              RDCLOCK=> To_X01Z(READ_CLK),
574
--              RDCLKEN=> To_X01Z(READ_CLK_ENABLE),
575
--              WRCLOCK=> To_X01Z(WRITE_CLK),
576
--             WRCLKEN=> To_X01Z(WRITE_CLK_ENABLE)
577
--);
578
 
579
 
580
DATA_OUT_64 <= To_bitvector(DATA_OUT_AUX(63 downto 32) & DATA_OUT_AUX(31 downto 0));
581
WRITE_CLK <= CLK;
582
READ_CLK <= CLK;
583
ENABLE_WRITE_MSB <= ENABLE_WRITE_INT and not(DECODING_WRITE_ADDRESS(0)) and WAITN; -- if wait active do not write
584
ENABLE_WRITE_LSB <= ENABLE_WRITE_INT and DECODING_WRITE_ADDRESS(0) and WAITN;
585
ENABLE_WRITE<= ENABLE_WRITE_INT and WAITN;
586
ENABLE_READ <= ENABLE_READ_INT and not(UNDERFLOW);
587
WRITE_CLK_ENABLE <= ENABLE_WRITE_INT;
588
READ_CLK_ENABLE <= ENABLE_READ;
589
START_ENGINE <= not(ENABLE_READ_INT);
590
 
591
 
592
end STRUCTURAL;

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