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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [bit_utils.vhd] - Blame information for rev 8

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1 8 eejlny 
-------------------------------------------------------------------------------
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--
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-- Copyright (c) 1994 by AT&T. All rights reserved.
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--
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-- This source file may be used and distributed without restriction
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-- provided that this copyright statement is not removed from the file
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-- and that any derivative work contains this copyright notice.
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--
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-- Package name: BIT_UTILS
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-- File name   : bit_utils.vhdl
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--
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-- Updates:
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--D  sccsid @(#)bit_utils.vhdl  1.2 daisy(C) 2/13/95 /files1/SCCS.model/bvhdl/vhdl_packages/dzx/src/s.bit_utils.vhdl
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-------------------------------------------------------------------------------
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package Bit_Utils is
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    ---------------------------------------------------------------------
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    -- rising, falling clock edge and clock level detection functions: --
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    ---------------------------------------------------------------------
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    function  Rising_Edge  (signal clock_name : Bit)  return Boolean;
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    function  Falling_Edge (signal clock_name : Bit)  return Boolean;
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    function  High_Level    (signal clock_name : Bit)  return Boolean;
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    function  Low_Level     (signal clock_name : Bit)  return Boolean;
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    --------------------------
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    -- conversions routines --
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    --------------------------
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    function To_Bit    (b: Boolean) return Bit;
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    function To_Char   (l : Bit)  return Character;
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    function To_String (v : Bit_Vector) return String;
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    ----------------------------------
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    -- Boolean reduction functions: --
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    ----------------------------------
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    function And_Bits  (v: Bit_Vector) return Bit;
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    function Nand_Bits  (v: Bit_Vector) return Bit;
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    function Or_Bits   (v: Bit_Vector) return Bit;
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    function Nor_Bits   (v: Bit_Vector) return Bit;
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    function Xor_Bits  (v: Bit_Vector) return Bit;
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    function Xnor_Bits (v: Bit_Vector) return Bit;
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    -- preset / clear procedure:
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    procedure Preset_Clear (signal FF: out Bit_Vector; Pc_Value: Bit_Vector);
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    procedure Preset_Clear (signal FF: out Bit; Pc_Value: Bit);
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    attribute BUILT_IN: BOOLEAN;                                  --D
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    attribute BUILT_IN of Rising_Edge: function is TRUE;          --D
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    attribute BUILT_IN of Falling_Edge: function is TRUE;         --D
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    attribute BUILT_IN of High_Level: function is TRUE;           --D
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    attribute BUILT_IN of LOw_Level: function is TRUE;            --D
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    attribute BUILT_IN of To_Bit            : function is TRUE;   --D
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    attribute BUILT_IN of To_Char           : function is TRUE;   --D
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    attribute BUILT_IN of To_String         : function is TRUE;   --D
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    attribute BUILT_IN of And_Bits: function is TRUE;             --D
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    attribute BUILT_IN of Nand_Bits: function is TRUE;            --D
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    attribute BUILT_IN of Or_Bits: function is TRUE;              --D
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    attribute BUILT_IN of Nor_Bits: function is TRUE;             --D
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    attribute BUILT_IN of Xor_Bits: function is TRUE;             --D
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    attribute BUILT_IN of Xnor_Bits: function is TRUE;            --D
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   attribute BUILT_IN of Preset_Clear: procedure is TRUE;         --D
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end Bit_Utils;
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 --D  sccsid @(#)bit_utils-body.vhdl    1.2 daisy(C) 2/13/95 /files1/SCCS.model/bvhdl/vhdl_packages/dzx/src/s.bit_utils-body.vhdl
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-------------------------------------------------------------------------------
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--    File: Bit_Utils
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--
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-------------------------------------------------------------------------------
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package body Bit_Utils is
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  -- contains the subprogram definitions for subprograms declared above.
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    ---------------------------------------------------------------------
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    -- rising, falling clock edge and clock level detection functions: --
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    ---------------------------------------------------------------------
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    function Rising_Edge (signal clock_name: Bit) return Boolean is
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    begin
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      return (clock_name = '1') and (clock_name'event);
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    end Rising_Edge;
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    function Falling_Edge (signal clock_name: Bit) return Boolean is
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    begin
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      return (clock_name = '0') and (clock_name'event);
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    end Falling_Edge;
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    function High_Level (signal clock_name: Bit) return Boolean is
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    begin
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      return (clock_name = '1');
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    end High_Level;
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    function Low_Level (signal clock_name: Bit) return Boolean is
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    begin
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      return (clock_name = '0');
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    end Low_Level;
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    -------------------------
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    -- Conversion routines --
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    -------------------------
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    function To_Bit (b: Boolean) return Bit is
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    begin
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      case b is
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        when FALSE => return '0';
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        when TRUE  => return '1';
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      end case;
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    end To_Bit;
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    function To_Char (l: Bit) return Character is
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    begin
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      case l is
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        when '0' => return '0';
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        when '1' => return '1';
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      end case;
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    end To_Char;
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    function To_String (v: Bit_Vector) return String is
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      variable ret: String (v'range);
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    begin
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      for j in ret'range loop
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        ret(j) := To_Char(v(j));
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      end loop;
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      return ret;
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    end To_String;
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  -----------------------------------
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  -- Boolean reduction functions:  --
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  -----------------------------------
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  function And_Bits (v: Bit_Vector) return Bit is
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    variable ret: Bit :='1';
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  begin
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    for j in  v'range loop
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      ret := ret and v(j);
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    end loop;
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    return ret;
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  end And_Bits;
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  function Nand_Bits (v: Bit_Vector) return Bit is
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  begin
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    return (not And_Bits(v));
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  end Nand_Bits;
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  function Or_Bits (v: Bit_Vector) return Bit is
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    variable ret: Bit := '0';
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  begin
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    for j in v'range loop
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      ret := ret or v(j);
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    end loop;
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    return ret;
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  end Or_Bits;
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  function Nor_Bits (v: Bit_Vector) return Bit is
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  begin
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    return (not Or_Bits(v));
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  end Nor_Bits;
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  function Xor_Bits (v: Bit_Vector) return Bit is
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    variable ret: Bit := '0';
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  begin
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    for j in v'range loop
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      ret := ret xor v(j);
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    end loop;
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    return ret;
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  end Xor_Bits;
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  function Xnor_Bits (v: Bit_Vector) return Bit is
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  begin
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    return (not Xor_Bits (v));
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  end Xnor_Bits;
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  -- preset / clear procedure:
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  procedure PRESET_CLEAR (signal FF: out BIT_VECTOR; PC_VALUE: BIT_VECTOR) is
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  begin
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    FF <= PC_VALUE;
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  end;
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  procedure PRESET_CLEAR (signal FF: out BIT; PC_VALUE: BIT) is
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  begin
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    FF <= PC_VALUE;
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  end;
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end Bit_Utils;
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