OpenCores
URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [latch98.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 eejlny
--This library is free software; you can redistribute it and/or
2
--modify it under the terms of the GNU Lesser General Public
3
--License as published by the Free Software Foundation; either
4
--version 2.1 of the License, or (at your option) any later version.
5
 
6
--This library is distributed in the hope that it will be useful,
7
--but WITHOUT ANY WARRANTY; without even the implied warranty of
8
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
9
--Lesser General Public License for more details.
10
 
11
--You should have received a copy of the GNU Lesser General Public
12
--License along with this library; if not, write to the Free Software
13
--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
14
 
15
-- e_mail : j.l.nunez-yanez@byacom.co.uk
16
 
17
---------------------------------
18
--  ENTITY       = LATCH98     --
19
--  version      = 1.0         --
20
--  last update  = 1/06/01    --
21
--  author       = Jose Nunez  --
22
---------------------------------
23
 
24
 
25
-- FUNCTION
26
-- 99 bit latch
27
 
28
 
29
-- PIN LIST
30
-- D_IN  = input data bus
31
-- CLEAR = asynchronous clear of latch
32
-- CLK   = master clock
33
-- D_OUT = output data bus
34
 
35
library ieee,dzx;
36
use ieee.std_logic_1164.all;
37
 
38
 
39
entity LATCH98 is
40
port
41
(
42
        D_IN : in bit_vector(97 downto 0);
43
        CLEAR : in bit;
44
        RESET : in bit;
45
        CLK : in bit;
46
        D_OUT : out bit_vector(97 downto 0)
47
);
48
 
49
 
50
end LATCH98;
51
 
52
 
53
architecture FLIP_FLOP of LATCH98 is
54
 
55
begin
56
 
57
FLOP : process (CLK,CLEAR)
58
begin
59
if (CLEAR = '0') then
60
    D_OUT <= "00" & x"000000000000000000000000";
61
elsif ((CLK'event) and (CLK = '1')) then
62
        if (RESET = '0') then
63
        D_OUT <= "00" & x"000000000000000000000000";
64
    else
65
                D_OUT <= D_IN;
66
    end if;
67
end if;
68
end process FLOP;
69
 
70
end FLIP_FLOP; -- end of architecture
71
 
72
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.