OpenCores
URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [reg_file_c.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 eejlny
--This library is free software; you can redistribute it and/or
2
--modify it under the terms of the GNU Lesser General Public
3
--License as published by the Free Software Foundation; either
4
--version 2.1 of the License, or (at your option) any later version.
5
 
6
--This library is distributed in the hope that it will be useful,
7
--but WITHOUT ANY WARRANTY; without even the implied warranty of
8
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
9
--Lesser General Public License for more details.
10
 
11
--You should have received a copy of the GNU Lesser General Public
12
--License along with this library; if not, write to the Free Software
13
--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
14
 
15
-- e_mail : j.l.nunez-yanez@byacom.co.uk
16
 
17
------------------------------------------
18
--  ENTITY       = REG_FILE             --
19
--  version      = 1.0                      --
20
--  last update  = 11/09/00         --
21
--  author       = Jose Nunez           --
22
------------------------------------------
23
 
24
 
25
-- FUNCTION
26
-- 16 bit wide treshold register
27
 
28
 
29
--  PIN LIST
30
 
31
 
32
--  DIN   = 16 bit input data
33
 
34
--  ADDRESS = 2 bit to address 
35
 
36
--  RW = read and write
37
 
38
--  ENABLE = enable the load
39
--  CLEAR = asynchronous clear of register
40
--  CLK   = clock
41
--  DOUT  = 16 bit output of flip-flops
42
 
43
--  C_BS_OUT = compressed block size 
44
 
45
--  U_BS_OUT = uncompressed block size
46
 
47
--  START_C = start the compression engine
48
 
49
--  START_D = start the decompression engine
50
 
51
--  STOP = stop the process
52
 
53
--  THRESHOLD_LEVEL = the threshold level of the buffers
54
 
55
 
56
 
57
library ieee,dzx;
58
use ieee.std_logic_1164.all;
59
 
60
 
61
entity REG_FILE_C is
62
port
63
(
64
      DIN : in bit_vector(31 downto 0);
65
      ADDRESS : in bit_vector(1 downto 0);
66
      RW : in bit;
67
      CLEAR_CR : in bit;
68
      FINISH : in bit;
69
      C_BS_IN : in bit_vector(31 downto 0);
70
          CRC_IN : in bit_vector(31 downto 0);
71
      ENABLE : in bit;
72
      CLEAR : in bit;
73
      CLK : in bit;
74
      DOUT : out std_logic_vector(31 downto 0);
75
          U_BS_OUT : out bit_vector(31 downto 0);
76
          CRC_OUT : out bit_vector(31 downto 0);
77
          START_C : out bit;
78
          STOP :out bit;
79
          MODE : out bit;
80
          THRESHOLD_LEVEL : out bit_vector(8 downto 0)
81
 
82
);
83
end REG_FILE_C;
84
 
85
 
86
architecture LATCH of REG_FILE_C is
87
 
88
component CONTROL_REG
89
port
90
(
91
      DIN : in bit_vector(31 downto 0);
92
      ENABLE : in bit;
93
      CLEAR : in bit;
94
      CLK : in bit;
95
      DOUT : out bit_vector(31 downto 0)
96
);
97
end component;
98
 
99
type TYPE_ARRAY is array(3 downto 0) of bit_vector(31 downto 0);
100
signal ARRAY_OUT : TYPE_ARRAY;
101
 
102
signal ENABLE_INT : bit_vector(3 downto 0);
103
signal ENABLE_CODE : bit_vector(3 downto 0);
104
 
105
 
106
signal ENABLE_REG_CBS : bit;
107
signal DIN_REG_CBS: bit_vector(31 downto 0);
108
 
109
signal ENABLE_REG_CRC : bit;
110
signal DIN_REG_CRC: bit_vector(31 downto 0);
111
 
112
 
113
signal ENABLE_REG_CR : bit;
114
signal DIN_REG_CR: bit_vector(31 downto 0);
115
 
116
 
117
 
118
 
119
begin
120
 
121
ENABLE_CODE <= ADDRESS & RW & ENABLE;
122
 
123
-- RW write =0
124
-- ENABLE active =0
125
 
126
WRITE : process(ENABLE_CODE)
127
begin
128
case ENABLE_CODE is
129
    when "0000" => ENABLE_INT <= "0001";
130
    when "0100" => ENABLE_INT <= "0010";
131
    when "1000" => ENABLE_INT <= "0100";
132
        when "1100" => ENABLE_INT <= "1000";
133
    when others => ENABLE_INT <= "0000";
134
end case;
135
end process WRITE;
136
 
137
READ : process(ENABLE_CODE, ARRAY_OUT)
138
begin
139
case ENABLE_CODE is
140
    when "0010" => DOUT <= To_X01Z(ARRAY_OUT(0));
141
    when "0110" => DOUT <= To_X01Z(ARRAY_OUT(1));
142
    when "1010" => DOUT <= To_X01Z(ARRAY_OUT(2));
143
        when "1110" => DOUT <= To_X01Z(ARRAY_OUT(3));
144
    when others => DOUT  <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
145
end case;
146
end process READ;
147
 
148
 
149
 
150
REG_CR : CONTROL_REG
151
 
152
port map ( DIN => DIN_REG_CR,
153
 
154
      ENABLE => ENABLE_REG_CR,
155
 
156
      CLEAR => CLEAR,
157
 
158
      CLK => CLK,
159
 
160
      DOUT => ARRAY_OUT(0));
161
 
162
 
163
 
164
 
165
REG_UBS : CONTROL_REG
166
 
167
port map ( DIN => DIN,
168
      ENABLE => ENABLE_INT(1),
169
      CLEAR => CLEAR,
170
      CLK => CLK,
171
      DOUT => ARRAY_OUT(1));
172
 
173
 
174
 
175
REG_CBS : CONTROL_REG
176
port map ( DIN => DIN_REG_CBS,
177
      ENABLE => ENABLE_REG_CBS,
178
      CLEAR => CLEAR,
179
      CLK => CLK,
180
      DOUT => ARRAY_OUT(2));
181
 
182
REG_CRC : CONTROL_REG
183
port map ( DIN => DIN_REG_CRC,
184
      ENABLE => ENABLE_REG_CRC,
185
      CLEAR => CLEAR,
186
      CLK => CLK,
187
      DOUT => ARRAY_OUT(3));
188
 
189
 
190
 
191
 
192
ENABLE_REG_CBS <= ENABLE_INT(2) when FINISH = '1' else '1';
193
ENABLE_REG_CRC <= ENABLE_INT(3) when FINISH = '1' else '1';
194
DIN_REG_CBS <= DIN when FINISH = '1' else C_BS_IN;
195
DIN_REG_CRC <= DIN when FINISH = '1' else CRC_IN;
196
 
197
 
198
ENABLE_REG_CR <= ENABLE_INT(0) when CLEAR_CR = '0' else '1'; -- clear the CR at the end of the compression phase
199
 
200
DIN_REG_CR <= DIN when CLEAR_CR = '0' else "11111111111111111111111111111111";  -- clear the CR
201
 
202
 
203
CRC_OUT <= ARRAY_OUT(3);
204
U_BS_OUT <= ARRAY_OUT(1);
205
START_C <=  ARRAY_OUT(0)(13) or ARRAY_OUT(0)(15); -- if both zeros engage compression engine
206
MODE <= ARRAY_OUT(0)(3) or ARRAY_OUT(0)(13) or ARRAY_OUT(0)(15); -- bit 3 indicates (0) test mode or (1) full-duplex mode
207
 
208
-- if three zeros engage test mode
209
 
210
STOP <= ARRAY_OUT(0)(14);
211
THRESHOLD_LEVEL <= ARRAY_OUT(0)(11 downto 4) & '0';
212
 
213
 
214
 
215
end LATCH;
216
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.