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Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [Makefile] - Blame information for rev 22

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GHDL:=/opt/ghdl/ghdl_mcode/translate/ghdldrv/ghdl_mcode
 
SOURCE:= ../../util/file/hexio.vhdl \
        ../../components/multiplexer/MUX.vhdl \
        generic_memory_block.vhdl \
        ram_parts.vhdl \
        RAM.vhdl \
        tb_generic_ram.vhdl
 
tb_generic:
        $(GHDL) -a $(SOURCE)
        $(GHDL) -e tb_generic_ram
 
# vim: set tw=0:

Line No.	Rev	Author	Line
1	22	lcdsgmtr	`GHDL:=/opt/ghdl/ghdl_mcode/translate/ghdldrv/ghdl_mcode`
2
3			`SOURCE:= ../../util/file/hexio.vhdl \`
4			`../../components/multiplexer/MUX.vhdl \`
5			`generic_memory_block.vhdl \`
6			`ram_parts.vhdl \`
7			`RAM.vhdl \`
8			`tb_generic_ram.vhdl`
9
10	19	lcdsgmtr	`tb_generic:`
11	22	lcdsgmtr	`$(GHDL) -a $(SOURCE)`
12			`$(GHDL) -e tb_generic_ram`
13	19	lcdsgmtr
14			`# vim: set tw=0:`

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Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [Makefile] - Blame information for rev 22