Subversion Repositories xucpu

-- This is the architecture of the board

-- It defines the bus system and is used as the main structure

-- to add devices.

-- These devices can be:

-- - Memory

-- - Cache controller

-- - CPU

-- - Input devices

-- - Output devices

-- The main goal of the system is to provide the bus, the bus

-- controller for arbitration between bus masters, the control

-- signals, the data and address signals, the data protocol

-- and the address decoding.

-- It should be possible to generate this file based upon a

-- description of the different devices.

ARCHITECTURE Structural OF board IS

  -- System constants

  CONSTANT nr_of_masters : INTEGER := 2;

  CONSTANT nr_of_devices : INTEGER := 5;

  CONSTANT addr_width : INTEGER := 15;

  CONSTANT data_width : INTEGER := 16;

  -- Definition of bus signals

  SIGNAL data_bus    : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL address_bus : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL bus_read    : STD_LOGIC;

  SIGNAL bus_write   : STD_LOGIC;

  SIGNAL bus_wait    : STD_LOGIC;

  SIGNAL bus_ack     : STD_LOGIC;

  -- Interconnection signals

  TYPE data_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);

  SIGNAL device_data_out : data_bus_array(0 TO nr_of_devices - 1);

  TYPE address_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

  SIGNAL device_address_out : address_bus_array(0 TO nr_of_masters - 1);

  -- Board level components

  -- Clock buffer

  SIGNAL clk : STD_LOGIC := '0';

  -- From asynchronous reset to synchronous reset

  SIGNAL rst : STD_LOGIC := '0';

  -- Definition of components related to the bus

  COMPONENT data_mux IS

    PORT (

      data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0));

  END COMPONENT data_mux;

  COMPONENT address_mux IS

    PORT (

      address_in : IN STD_LOGIC_VECTOR(14 DOWNTO 0));

  END COMPONENT address_mux;

  COMPONENT address_decoder IS

    PORT (

      address_in : IN STD_LOGIC_VECTOR(14 DOWNTO 0));

  END COMPONENT address_decoder;

  COMPONENT bus_arbiter IS

    PORT (

      clk        : IN  STD_LOGIC;

      rst        : IN  STD_LOGIC;

      rd_rq      : IN  STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);

      wr_rq      : IN  STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);

      master_ack : OUT STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0));

  END COMPONENT bus_arbiter;

  SIGNAL rd_rq      : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);

  SIGNAL wr_rq      : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);

  SIGNAL master_ack : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);

  -- Definition of master devices attached to the bus

  COMPONENT icache IS

    PORT (

      clk        : IN  STD_LOGIC;

      rst        : IN  STD_LOGIC;

      data_in    : IN  STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);

      addr_out   : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

      data_rd    : OUT STD_LOGIC;

      bus_wait   : IN  STD_LOGIC;

      master_ack : IN  STD_LOGIC);

  END COMPONENT icache;

  COMPONENT dcache IS

    PORT (

      clk        : IN  STD_LOGIC;

      rst        : IN  STD_LOGIC;

      data_in    : IN  STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);

      data_out   : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);

      addr_out   : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

      data_rd    : OUT STD_LOGIC;

      data_wr    : OUT STD_LOGIC;

      bus_wait   : IN  STD_LOGIC;

      master_ack : IN  STD_LOGIC);

  END COMPONENT dcache;

  -- Definition of io devices attached to the bus

  COMPONENT led_out IS

    PORT (

      clk      : IN  STD_LOGIC;

      rst      : IN  STD_LOGIC;

      data_in  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);

      addr_in  : IN  STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

      port_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

  END COMPONENT led_out;

  COMPONENT button_in IS

    PORT (

      clk      : IN  STD_LOGIC;

      rst      : IN  STD_LOGIC;

      data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

      addr_in  : IN  STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

      port_in  : IN  STD_LOGIC_VECTOR(4 DOWNTO 0));

  END COMPONENT button_in;

  COMPONENT switch_in IS

    PORT (

      clk      : IN  STD_LOGIC;

      rst      : IN  STD_LOGIC;

      data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

      addr_in  : IN  STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);

      port_in  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0));

  END COMPONENT switch_in;

BEGIN  -- ARCHITECTURE Structural

  -- Mapping of bus related components

  bus_arbiter_1 : bus_arbiter

    PORT MAP (

      clk        => clk,

      rst        => rst,

      rd_rq      => rd_rq,

      wr_rq      => wr_rq,

      master_ack => master_ack);

  -- Mapping of system devices

  -- Main memory

  -- Instruction cache

  icache_0 : icache

    PORT MAP (

      clk        => clk,

      rst        => rst,

      data_in    => data_bus,

      addr_out   => device_address_out(0),

      data_rd    => rd_rq(0),

      bus_wait   => bus_wait,

      master_ack => master_ack(0));

  -- Data cache

  dcache_1 : dcache

    PORT MAP (

      clk        => clk,

      rst        => rst,

      data_in    => data_bus,

      data_out   => device_data_out(1),

      addr_out   => device_address_out(1),

      data_rd    => rd_rq(1),

      data_wr    => wr_rq(1),

      bus_wait   => bus_wait,

      master_ack => master_ack(0));

  -- LED output device

  led_out_2 : led_out

    PORT MAP (

      clk      => clk,

      rst      => rst,

      data_in  => data_bus(7 DOWNTO 0),

      addr_in  => address_bus,

      port_out => led);

  -- Push button input device

  button_in_3 : button_in

    PORT MAP (

      clk      => clk,

      rst      => rst,

      data_out => device_data_out(3)(7 DOWNTO 0),

      addr_in  => address_bus,

      port_in  => button);

  -- Slide switch input device

  switch_in_4 : switch_in

    PORT MAP (

      clk      => clk,

      rst      => rst,

      data_out => device_data_out(4)(7 DOWNTO 0),

      addr_in  => address_bus,

      port_in  => switch);

  -- Serial communication device

  -- MAC device

  -- DVI device

  -- Character based device

END ARCHITECTURE Structural;