1 |
115 |
dgisselq |
#define XULA25
|
2 |
75 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
3 |
4 |
dgisselq |
//
|
4 |
|
|
// Filename: busmaster_tb.cpp
|
5 |
|
|
//
|
6 |
|
|
// Project: FPGA library development (XuLA2 development board)
|
7 |
|
|
//
|
8 |
|
|
// Purpose: This is piped version of the testbench for the busmaster
|
9 |
|
|
// verilog code. The busmaster code is designed to be a complete
|
10 |
75 |
dgisselq |
// code set implementing all of the functionality of the XESS XuLA2
|
11 |
|
|
// development board. If done well, the programs talking to this one
|
12 |
|
|
// should be able to talk to the board and apply the same tests to the
|
13 |
|
|
// board itself.
|
14 |
4 |
dgisselq |
//
|
15 |
75 |
dgisselq |
// Creator: Dan Gisselquist, Ph.D.
|
16 |
|
|
// Gisselquist Technology, LLC
|
17 |
4 |
dgisselq |
//
|
18 |
75 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
19 |
4 |
dgisselq |
//
|
20 |
75 |
dgisselq |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
21 |
4 |
dgisselq |
//
|
22 |
75 |
dgisselq |
// This program is free software (firmware): you can redistribute it and/or
|
23 |
|
|
// modify it under the terms of the GNU General Public License as published
|
24 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
25 |
|
|
// your option) any later version.
|
26 |
|
|
//
|
27 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
28 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
29 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
30 |
|
|
// for more details.
|
31 |
|
|
//
|
32 |
|
|
// You should have received a copy of the GNU General Public License along
|
33 |
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
34 |
|
|
// target there if the PDF file isn't present.) If not, see
|
35 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
36 |
|
|
//
|
37 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
38 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
39 |
|
|
//
|
40 |
|
|
//
|
41 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
42 |
|
|
//
|
43 |
|
|
//
|
44 |
4 |
dgisselq |
#include <signal.h>
|
45 |
|
|
#include <time.h>
|
46 |
112 |
dgisselq |
#include <ctype.h>
|
47 |
4 |
dgisselq |
|
48 |
|
|
#include "verilated.h"
|
49 |
|
|
#include "Vbusmaster.h"
|
50 |
|
|
|
51 |
|
|
#include "testb.h"
|
52 |
|
|
// #include "twoc.h"
|
53 |
|
|
#include "pipecmdr.h"
|
54 |
|
|
#include "qspiflashsim.h"
|
55 |
|
|
#include "sdramsim.h"
|
56 |
75 |
dgisselq |
#include "sdspisim.h"
|
57 |
112 |
dgisselq |
#include "uartsim.h"
|
58 |
4 |
dgisselq |
|
59 |
|
|
#include "port.h"
|
60 |
|
|
|
61 |
|
|
// Add a reset line, since Vbusmaster doesn't have one
|
62 |
|
|
class Vbusmasterr : public Vbusmaster {
|
63 |
|
|
public:
|
64 |
|
|
int i_rst;
|
65 |
|
|
virtual ~Vbusmasterr() {}
|
66 |
|
|
};
|
67 |
|
|
|
68 |
|
|
// No particular "parameters" need definition or redefinition here.
|
69 |
|
|
class BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {
|
70 |
|
|
public:
|
71 |
|
|
unsigned long m_tx_busy_count;
|
72 |
|
|
QSPIFLASHSIM m_flash;
|
73 |
75 |
dgisselq |
SDSPISIM m_sdcard;
|
74 |
4 |
dgisselq |
SDRAMSIM m_sdram;
|
75 |
113 |
dgisselq |
unsigned m_last_led, m_last_pic, m_last_tx_state;
|
76 |
4 |
dgisselq |
time_t m_start_time;
|
77 |
75 |
dgisselq |
bool m_last_writeout;
|
78 |
112 |
dgisselq |
UARTSIM m_uart;
|
79 |
113 |
dgisselq |
int m_last_bus_owner, m_busy;
|
80 |
4 |
dgisselq |
|
81 |
112 |
dgisselq |
BUSMASTER_TB(void) : PIPECMDR(FPGAPORT), m_uart(FPGAPORT+1) {
|
82 |
4 |
dgisselq |
m_start_time = time(NULL);
|
83 |
113 |
dgisselq |
m_last_pic = 0;
|
84 |
|
|
m_last_tx_state = 0;
|
85 |
4 |
dgisselq |
}
|
86 |
|
|
|
87 |
|
|
void reset(void) {
|
88 |
|
|
m_core->i_clk = 1;
|
89 |
|
|
m_core->eval();
|
90 |
|
|
}
|
91 |
|
|
|
92 |
75 |
dgisselq |
void setsdcard(const char *fn) {
|
93 |
|
|
m_sdcard.load(fn);
|
94 |
96 |
dgisselq |
|
95 |
|
|
printf("LOADING SDCARD FROM: \'%s\'\n", fn);
|
96 |
75 |
dgisselq |
}
|
97 |
|
|
|
98 |
4 |
dgisselq |
void tick(void) {
|
99 |
75 |
dgisselq |
int flash_miso, sdcard_miso;
|
100 |
|
|
|
101 |
4 |
dgisselq |
if ((m_tickcount & ((1<<28)-1))==0) {
|
102 |
|
|
double ticks_per_second = m_tickcount;
|
103 |
47 |
dgisselq |
time_t seconds_passed = time(NULL)-m_start_time;
|
104 |
|
|
if (seconds_passed != 0) {
|
105 |
4 |
dgisselq |
ticks_per_second /= (double)(time(NULL) - m_start_time);
|
106 |
|
|
printf(" ******** %.6f TICKS PER SECOND\n",
|
107 |
|
|
ticks_per_second);
|
108 |
47 |
dgisselq |
}
|
109 |
4 |
dgisselq |
}
|
110 |
|
|
|
111 |
|
|
// Set up the bus before any clock tick
|
112 |
|
|
m_core->i_clk = 1;
|
113 |
75 |
dgisselq |
flash_miso = (m_flash(m_core->o_sf_cs_n,
|
114 |
|
|
m_core->o_spi_sck,
|
115 |
|
|
m_core->o_spi_mosi)&0x02)?1:0;
|
116 |
115 |
dgisselq |
#ifdef XULA25
|
117 |
75 |
dgisselq |
sdcard_miso = m_sdcard(m_core->o_sd_cs_n, m_core->o_spi_sck,
|
118 |
|
|
m_core->o_spi_mosi);
|
119 |
117 |
dgisselq |
#else
|
120 |
|
|
sdcard_miso = 1;
|
121 |
115 |
dgisselq |
#endif
|
122 |
75 |
dgisselq |
|
123 |
|
|
if ((m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
|
124 |
|
|
m_core->i_spi_miso = 1;
|
125 |
|
|
else if ((!m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
|
126 |
|
|
m_core->i_spi_miso = flash_miso;
|
127 |
|
|
else if ((m_core->o_sf_cs_n)&&(!m_core->o_sd_cs_n))
|
128 |
|
|
m_core->i_spi_miso = sdcard_miso;
|
129 |
|
|
else
|
130 |
|
|
assert((m_core->o_sf_cs_n)||(m_core->o_sd_cs_n));
|
131 |
|
|
|
132 |
4 |
dgisselq |
m_core->i_ram_data = m_sdram(1,
|
133 |
|
|
m_core->o_ram_cke, m_core->o_ram_cs_n,
|
134 |
|
|
m_core->o_ram_ras_n, m_core->o_ram_cas_n,
|
135 |
|
|
m_core->o_ram_we_n, m_core->o_ram_bs,
|
136 |
|
|
m_core->o_ram_addr, m_core->o_ram_drive_data,
|
137 |
|
|
m_core->o_ram_data);
|
138 |
112 |
dgisselq |
|
139 |
|
|
m_core->i_rx_uart = m_uart(m_core->o_tx_uart,
|
140 |
|
|
m_core->v__DOT__serialport__DOT__r_setup);
|
141 |
4 |
dgisselq |
PIPECMDR::tick();
|
142 |
|
|
|
143 |
118 |
dgisselq |
// #define DEBUGGING_OUTPUT
|
144 |
113 |
dgisselq |
#ifdef DEBUGGING_OUTPUT
|
145 |
4 |
dgisselq |
bool writeout = false;
|
146 |
113 |
dgisselq |
/*
|
147 |
|
|
if (m_core->v__DOT__sdram__DOT__r_pending)
|
148 |
|
|
writeout = true;
|
149 |
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[0])
|
150 |
|
|
writeout = true;
|
151 |
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[1])
|
152 |
|
|
writeout = true;
|
153 |
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[2])
|
154 |
|
|
writeout = true;
|
155 |
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[3])
|
156 |
|
|
writeout = true;
|
157 |
|
|
*/
|
158 |
75 |
dgisselq |
|
159 |
117 |
dgisselq |
// if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
|
160 |
|
|
// writeout = true;
|
161 |
113 |
dgisselq |
/*
|
162 |
|
|
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
|
163 |
|
|
writeout = true;
|
164 |
|
|
if (m_core->v__DOT__genbus__DOT__exec_stb)
|
165 |
|
|
writeout = true;
|
166 |
|
|
*/
|
167 |
|
|
|
168 |
117 |
dgisselq |
// if ((m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
|
169 |
|
|
// &&(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction == 0x7883ffff))
|
170 |
|
|
// m_busy+=2;
|
171 |
|
|
// else if (m_busy > 0) m_busy--;
|
172 |
113 |
dgisselq |
#define v__DOT__wb_addr v__DOT__dwb_addr
|
173 |
|
|
#define v__DOT__dwb_stall v__DOT__wb_stall
|
174 |
|
|
#define v__DOT__dwb_ack v__DOT__wb_ack
|
175 |
|
|
#define v__DOT__wb_cyc v__DOT__dwb_cyc
|
176 |
|
|
#define v__DOT__wb_stb v__DOT__dwb_stb
|
177 |
|
|
#define v__DOT__wb_we v__DOT__dwb_we
|
178 |
|
|
#define v__DOT__dwb_idata v__DOT__wb_idata
|
179 |
|
|
#define v__DOT__wb_data v__DOT__dwb_odata
|
180 |
|
|
|
181 |
|
|
if ((!m_core->v__DOT__zippy__DOT__cmd_halt)
|
182 |
|
|
&&(!m_core->v__DOT__zippy__DOT__thecpu__DOT__sleep))
|
183 |
|
|
writeout = true;
|
184 |
|
|
// if (m_core->v__DOT__uart_tx_int)
|
185 |
|
|
// writeout = true;
|
186 |
|
|
#ifdef XULA25
|
187 |
|
|
if (m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_any)
|
188 |
|
|
writeout = true;
|
189 |
|
|
#endif
|
190 |
|
|
|
191 |
|
|
#ifdef XULA25
|
192 |
|
|
unsigned this_pic = ((m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_enable)<<16) |
|
193 |
|
|
(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_state);
|
194 |
|
|
#else
|
195 |
|
|
unsigned this_pic = 0;
|
196 |
|
|
#endif
|
197 |
|
|
|
198 |
|
|
// if (this_pic != m_last_pic)
|
199 |
|
|
// writeout = true;
|
200 |
|
|
unsigned tx_state = ((m_core->v__DOT__serialport__DOT__txmod__DOT__zero_baud_counter)<<20)
|
201 |
|
|
|((m_core->v__DOT__serialport__DOT__txmod__DOT__r_busy)<<16)
|
202 |
|
|
|((m_core->v__DOT__serialport__DOT__txmod__DOT__lcl_data)<<8)
|
203 |
|
|
|((m_core->v__DOT__serialport__DOT__txmod__DOT__baud_counter&0x0f)<<4)
|
204 |
|
|
|(m_core->v__DOT__serialport__DOT__txmod__DOT__state);
|
205 |
117 |
dgisselq |
/*
|
206 |
113 |
dgisselq |
if (tx_state != m_last_tx_state)
|
207 |
|
|
writeout = true;
|
208 |
117 |
dgisselq |
*/
|
209 |
113 |
dgisselq |
int bus_owner = m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner;
|
210 |
|
|
bus_owner |= (m_core->v__DOT__wbu_cyc)?2:0;
|
211 |
|
|
bus_owner |= (m_core->v__DOT__dwb_cyc)?4:0;
|
212 |
|
|
bus_owner |= (m_core->v__DOT__wb_cyc)?8:0;
|
213 |
|
|
bus_owner |= (m_core->v__DOT__wb_cyc)?16:0;
|
214 |
|
|
bus_owner |= (m_core->v__DOT__wbu_stb)?32:0;
|
215 |
|
|
bus_owner |= (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl)?64:0;
|
216 |
|
|
bus_owner |= (m_core->v__DOT__wb_stb)?128:0;
|
217 |
|
|
bus_owner |= (m_core->v__DOT____Vcellinp__wbu_zip_arbiter____pinNumber10)?256:0;
|
218 |
|
|
#ifdef XULA25
|
219 |
|
|
bus_owner |= (m_core->v__DOT__zippy__DOT__ext_cyc)?512:0;
|
220 |
|
|
#endif
|
221 |
117 |
dgisselq |
/*
|
222 |
113 |
dgisselq |
if (bus_owner != m_last_bus_owner)
|
223 |
|
|
writeout = true;
|
224 |
117 |
dgisselq |
*/
|
225 |
113 |
dgisselq |
/*
|
226 |
|
|
writeout = (writeout)||(m_core->i_rx_stb)
|
227 |
|
|
||((m_core->o_tx_stb)&&(!m_core->i_tx_busy));
|
228 |
|
|
writeout = (writeout)||(m_core->v__DOT____Vcellinp__genbus____pinNumber9);
|
229 |
|
|
writeout = (writeout)||(m_core->v__DOT__wb_stb);
|
230 |
|
|
writeout = (writeout)||(m_core->v__DOT__wb_err);
|
231 |
|
|
*/
|
232 |
|
|
|
233 |
75 |
dgisselq |
if ((writeout)||(m_last_writeout)) {
|
234 |
113 |
dgisselq |
m_last_bus_owner = bus_owner;
|
235 |
|
|
m_last_pic = this_pic;
|
236 |
|
|
m_last_tx_state = tx_state;
|
237 |
4 |
dgisselq |
printf("%08lx:", m_tickcount);
|
238 |
|
|
|
239 |
113 |
dgisselq |
/*
|
240 |
|
|
printf("%d/%02x %d/%02x%s ",
|
241 |
|
|
m_core->i_rx_stb, m_core->i_rx_data,
|
242 |
|
|
m_core->o_tx_stb, m_core->o_tx_data,
|
243 |
|
|
m_core->i_tx_busy?"/BSY":" ");
|
244 |
|
|
*/
|
245 |
|
|
|
246 |
|
|
printf("(%d/%d,%d/%d->%d),(%c:%d,%d->%d)|%c[%08x/%08x]@%08x %c%c%c",
|
247 |
|
|
m_core->v__DOT__wbu_cyc,
|
248 |
|
|
m_core->v__DOT____Vcellinp__wbu_zip_arbiter____pinNumber10,
|
249 |
|
|
m_core->v__DOT__dwb_cyc, // was zip_cyc
|
250 |
|
|
#ifdef XULA25
|
251 |
|
|
(m_core->v__DOT__zippy__DOT__ext_cyc),
|
252 |
|
|
#else
|
253 |
|
|
0,
|
254 |
|
|
#endif
|
255 |
|
|
m_core->v__DOT__wb_cyc,
|
256 |
|
|
//
|
257 |
|
|
m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
|
258 |
|
|
m_core->v__DOT__wbu_stb,
|
259 |
|
|
// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
|
260 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
|
261 |
|
|
m_core->v__DOT__wb_stb,
|
262 |
|
|
//
|
263 |
|
|
(m_core->v__DOT__wb_we)?'W':'R',
|
264 |
|
|
m_core->v__DOT__wb_data,
|
265 |
|
|
m_core->v__DOT__dwb_idata,
|
266 |
|
|
m_core->v__DOT__wb_addr,
|
267 |
|
|
(m_core->v__DOT__dwb_ack)?'A':
|
268 |
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
|
269 |
|
|
(m_core->v__DOT__dwb_stall)?'S':
|
270 |
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
|
271 |
|
|
(m_core->v__DOT__wb_err)?'E':'.');
|
272 |
|
|
|
273 |
|
|
/*
|
274 |
|
|
// UART-Wishbone bus converter debug lines
|
275 |
|
|
printf(" RUNWB %d:%09lx %d@0x%08x %3x %3x %d %d/%d/%d %d:%09lx",
|
276 |
|
|
m_core->v__DOT__genbus__DOT__fifo_in_stb,
|
277 |
|
|
m_core->v__DOT__genbus__DOT__fifo_in_word,
|
278 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
|
279 |
|
|
m_core->v__DOT__wbu_addr,
|
280 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
281 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed,
|
282 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__w_eow,
|
283 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__last_read_request,
|
284 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__last_ack,
|
285 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__zero_acks,
|
286 |
|
|
m_core->v__DOT__genbus__DOT__exec_stb,
|
287 |
|
|
m_core->v__DOT__genbus__DOT__exec_word);
|
288 |
|
|
*/
|
289 |
|
|
|
290 |
|
|
/*
|
291 |
|
|
// UART-Wishbone bus converter debug lines
|
292 |
|
|
printf(" WBU[%d,%3d,%3d]",
|
293 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
|
294 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
295 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed);
|
296 |
|
|
*/
|
297 |
|
|
|
298 |
|
|
/*
|
299 |
|
|
// SDRAM debug lines
|
300 |
|
|
printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
|
301 |
|
|
(m_core->v__DOT__sdram_sel)?'!':' ',
|
302 |
|
|
m_core->o_ram_cs_n, m_core->o_ram_ras_n,
|
303 |
|
|
m_core->o_ram_cas_n, m_core->o_ram_we_n,
|
304 |
|
|
m_core->o_ram_bs, m_core->o_ram_data,
|
305 |
|
|
(m_core->o_ram_drive_data)?'D':'-',
|
306 |
|
|
m_core->o_ram_addr,
|
307 |
|
|
(m_core->o_ram_addr>>10)&1,
|
308 |
|
|
m_core->i_ram_data,
|
309 |
|
|
(m_core->o_ram_drive_data)?'-':'V');
|
310 |
|
|
|
311 |
|
|
printf(" SD[%d,%d-%3x%d]",
|
312 |
|
|
m_core->v__DOT__sdram__DOT__r_state,
|
313 |
|
|
m_sdram.pwrup(),
|
314 |
|
|
m_core->v__DOT__sdram__DOT__refresh_clk,
|
315 |
|
|
m_core->v__DOT__sdram__DOT__need_refresh);
|
316 |
|
|
|
317 |
|
|
printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
|
318 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[0],
|
319 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[0],
|
320 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[1],
|
321 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[1],
|
322 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[2],
|
323 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[2],
|
324 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[3],
|
325 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[3],
|
326 |
|
|
m_core->v__DOT__sdram__DOT__clocks_til_idle,
|
327 |
|
|
m_core->v__DOT__sdram__DOT__r_barrell_ack);
|
328 |
|
|
|
329 |
|
|
printf(" %s%s%c[%08x@%06x]",
|
330 |
|
|
(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
|
331 |
|
|
(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
|
332 |
|
|
(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
|
333 |
|
|
(m_core->v__DOT__sdram__DOT__r_we)
|
334 |
|
|
?(m_core->v__DOT__sdram__DOT__r_data)
|
335 |
|
|
:(m_core->v__DOT__sdram_data),
|
336 |
|
|
(m_core->v__DOT__sdram__DOT__r_addr));
|
337 |
|
|
*/
|
338 |
|
|
|
339 |
|
|
// CPU Pipeline debugging
|
340 |
|
|
printf("%s%s%s%s%s%s%s%s%s%s%s",
|
341 |
|
|
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
|
342 |
|
|
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
|
343 |
|
|
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
|
344 |
|
|
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
|
345 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_halted)?"Z":"-",
|
346 |
|
|
(m_core->v__DOT__zippy__DOT__cpu_break)?"!":"-",
|
347 |
|
|
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
|
348 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__gie)?"G":"-",
|
349 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
|
350 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_valid)?"V":"-",
|
351 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_illegal)?"i":" ",
|
352 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
|
353 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"G":"-",
|
354 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"L":"-");
|
355 |
|
|
printf("|%s%s%s%s%s%s",
|
356 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?"D":"-",
|
357 |
|
|
(dcd_ce())?"d":"-",
|
358 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdA_stall)?"A":"-",
|
359 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdB_stall)?"B":"-",
|
360 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdF_stall)?"F":"-",
|
361 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_illegal)?"i":"-");
|
362 |
|
|
|
363 |
|
|
printf("|%s%s%s%s%s%s%s%s%s%s",
|
364 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
|
365 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
|
366 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_stall)?"s":"-",
|
367 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_illegal)?"i":"-",
|
368 |
117 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_op_break)?"B":"-",
|
369 |
113 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__genblk5__DOT__r_op_lock)?"L":"-",
|
370 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_op_pipe)?"P":"-",
|
371 |
117 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_break_pending)?"p":"-",
|
372 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_op_gie)?"G":"-",
|
373 |
113 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_alu)?"A":"-");
|
374 |
|
|
printf("|%s%s%s%s%s",
|
375 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_ce)?"a":"-",
|
376 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_stall)?"s":"-",
|
377 |
118 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__doalu__DOT__r_busy)?"B":"-",
|
378 |
117 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_gie)?"G":"-",
|
379 |
113 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_illegal)?"i":"-");
|
380 |
|
|
printf("|%s%s%s%2x %s%s%s %2d %2d",
|
381 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)?"M":"-",
|
382 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_ce)?"m":"-",
|
383 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__adf_ce_unconditional)?"!":"-",
|
384 |
|
|
(m_core->v__DOT__zippy__DOT__cmd_addr),
|
385 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__bus_err)?"BE":" ",
|
386 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
|
387 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ubus_err_flag)?"UB":" ",
|
388 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__rdaddr,
|
389 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__wraddr);
|
390 |
|
|
#ifdef XULA25
|
391 |
|
|
printf("|%s%s",
|
392 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__div_busy)?"D":"-",
|
393 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__div_error)?"E":"-");
|
394 |
|
|
#endif
|
395 |
|
|
printf("|%s%s[%2x]%08x",
|
396 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce)?"W":"-",
|
397 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_flags_ce)?"F":"-",
|
398 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
399 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl);
|
400 |
|
|
|
401 |
|
|
// Program counter debugging
|
402 |
|
|
printf(" PC0x%08x/%08x/%08x-%08x %s0x%08x",
|
403 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
404 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__ipc,
|
405 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__upc,
|
406 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
407 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ",
|
408 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc
|
409 |
|
|
);
|
410 |
|
|
// More in-depth
|
411 |
|
|
printf("[%c%08x,%c%08x,%c%08x]",
|
412 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?'D':'-',
|
413 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_pc,
|
414 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?'O':'-',
|
415 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__op_pc,
|
416 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_valid)?'A':'-',
|
417 |
117 |
dgisselq |
m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_pc);
|
418 |
|
|
|
419 |
|
|
/*
|
420 |
113 |
dgisselq |
// Prefetch debugging
|
421 |
|
|
printf(" [PC%08x,LST%08x]->[%d%s%s](%d,%08x/%08x)->%08x@%08x",
|
422 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
423 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__lastpc,
|
424 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc,
|
425 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
426 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"P":" ")
|
427 |
|
|
:((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"p":" "),
|
428 |
|
|
(!m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
429 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"l":" ")
|
430 |
|
|
:((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"L":" "),
|
431 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__isrc,
|
432 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_pc_cache,
|
433 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_last_cache,
|
434 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
435 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_pc);
|
436 |
117 |
dgisselq |
*/
|
437 |
113 |
dgisselq |
|
438 |
|
|
// Decode Stage debugging
|
439 |
|
|
// (nothing)
|
440 |
|
|
|
441 |
|
|
// Op Stage debugging
|
442 |
117 |
dgisselq |
// printf(" Op(%02x,%02x->%02x)",
|
443 |
|
|
// m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdOp,
|
444 |
|
|
// m_core->v__DOT__zippy__DOT__thecpu__DOT__opn,
|
445 |
|
|
// m_core->v__DOT__zippy__DOT__thecpu__DOT__opR);
|
446 |
113 |
dgisselq |
|
447 |
|
|
printf(" %s[%02x]=%08x(%08x)",
|
448 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce?"WR":"--",
|
449 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
450 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl,
|
451 |
|
|
#ifdef XULA25
|
452 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_spreg_vl
|
453 |
|
|
#else
|
454 |
|
|
|
455 |
|
|
#endif
|
456 |
|
|
);
|
457 |
|
|
printf(" Rid=(%d|%d)?%02x:%02x",
|
458 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_wr,
|
459 |
|
|
#ifdef XULA25
|
460 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__div_valid,
|
461 |
|
|
#else
|
462 |
|
|
0,
|
463 |
|
|
#endif
|
464 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_reg,
|
465 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_wreg);
|
466 |
|
|
|
467 |
|
|
// domem, the pipelined memory unit debugging
|
468 |
117 |
dgisselq |
/*
|
469 |
113 |
dgisselq |
printf(" M[%s@0x%08x]",
|
470 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)
|
471 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__opn&1)?"W":"R")
|
472 |
|
|
:"-",
|
473 |
|
|
#ifdef XULA25
|
474 |
|
|
m_core->v__DOT__zippy__DOT__cpu_addr
|
475 |
|
|
#else
|
476 |
|
|
|
477 |
|
|
#endif
|
478 |
|
|
);
|
479 |
117 |
dgisselq |
*/
|
480 |
|
|
|
481 |
|
|
/*
|
482 |
113 |
dgisselq |
printf("%s%s",
|
483 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__cyc)?"B":"-",
|
484 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_rdbusy)?"r":"-");
|
485 |
117 |
dgisselq |
*/
|
486 |
|
|
#ifdef XULA25
|
487 |
113 |
dgisselq |
printf(" %s-%s %04x/%04x",
|
488 |
|
|
(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_any)?"PIC":"pic",
|
489 |
|
|
(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_gie)?"INT":"( )",
|
490 |
|
|
m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_enable,
|
491 |
|
|
m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_state);
|
492 |
117 |
dgisselq |
#else
|
493 |
|
|
printf(" %s-%s %04x/%04x",
|
494 |
|
|
(m_core->v__DOT__runio__DOT__intcontroller__DOT__r_any)?"PIC":"pic",
|
495 |
|
|
(m_core->v__DOT__runio__DOT__intcontroller__DOT__r_gie)?"INT":"( )",
|
496 |
|
|
m_core->v__DOT__runio__DOT__intcontroller__DOT__r_int_enable,
|
497 |
|
|
m_core->v__DOT__runio__DOT__intcontroller__DOT__r_int_state);
|
498 |
|
|
#endif
|
499 |
113 |
dgisselq |
|
500 |
|
|
|
501 |
117 |
dgisselq |
/*
|
502 |
113 |
dgisselq |
printf(" %s",
|
503 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__cc_invalid_for_dcd)?"CCI":" ");
|
504 |
117 |
dgisselq |
*/
|
505 |
|
|
|
506 |
113 |
dgisselq |
/*
|
507 |
|
|
// Illegal instruction debugging
|
508 |
|
|
printf(" ILL[%s%s%s%s%s%s]",
|
509 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_err)?"WB":" ",
|
510 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_illegal)?"PF":" ",
|
511 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_illegal)?"DCD":" ",
|
512 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_illegal)?"OP":" ",
|
513 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_illegal)?"ALU":" ",
|
514 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ill_err_u)?"ILL":" ");
|
515 |
|
|
|
516 |
|
|
*/
|
517 |
|
|
|
518 |
|
|
/*
|
519 |
|
|
printf(" UART%08x/%d-%08x", m_last_tx_state,
|
520 |
|
|
m_core->v__DOT__serialport__DOT__txmod__DOT__zero_baud_counter,
|
521 |
|
|
m_core->v__DOT__serialport__DOT__txmod__DOT__baud_counter);
|
522 |
|
|
*/
|
523 |
|
|
|
524 |
|
|
// Debug some conditions
|
525 |
|
|
if (m_core->v__DOT__zippy__DOT__thecpu__DOT__ubreak)
|
526 |
|
|
printf(" BREAK");
|
527 |
|
|
// if (m_core->v__DOT__zippy__DOT__thecpu__DOT__w_switch_to_interrupt)
|
528 |
|
|
// printf(" TO-INT");
|
529 |
|
|
#ifdef XULA25
|
530 |
|
|
if (m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_interrupt)
|
531 |
|
|
printf(" INTERRUPT");
|
532 |
|
|
#endif
|
533 |
|
|
|
534 |
|
|
/*
|
535 |
|
|
printf(" SDSPI[%d,%d(%d),(%d)]",
|
536 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
|
537 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
538 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
|
539 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
|
540 |
|
|
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
|
541 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
|
542 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
|
543 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
|
544 |
|
|
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
|
545 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
|
546 |
|
|
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
|
547 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
|
548 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
|
549 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
|
550 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
|
551 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
|
552 |
|
|
);
|
553 |
|
|
printf(" CRC=%02x/%2d",
|
554 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
|
555 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
|
556 |
|
|
printf(" SPI(%d,%d,%d/%d,%d)->?",
|
557 |
|
|
m_core->o_sf_cs_n,
|
558 |
|
|
m_core->o_sd_cs_n,
|
559 |
|
|
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
|
560 |
|
|
m_core->o_spi_mosi);
|
561 |
|
|
|
562 |
|
|
printf(" CK=%d,LN=%d",
|
563 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
564 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
|
565 |
|
|
|
566 |
|
|
|
567 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
|
568 |
|
|
printf(" FIFO");
|
569 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
|
570 |
|
|
printf("-WR(%04x,%d,%d,%d)",
|
571 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
|
572 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
|
573 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
|
574 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
|
575 |
|
|
else
|
576 |
|
|
printf("-RD(%04x,%d,%d,%d)",
|
577 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
|
578 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
|
579 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
|
580 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
|
581 |
|
|
);
|
582 |
|
|
}
|
583 |
|
|
|
584 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_rd)
|
585 |
|
|
printf(" LL-RD");
|
586 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr)
|
587 |
|
|
printf(" LL-WR");
|
588 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_have_start_token)
|
589 |
|
|
printf(" START-TOK");
|
590 |
|
|
printf(" %3d/%02x",
|
591 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_addr,
|
592 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_byte&0x0ff);
|
593 |
|
|
*/
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
/*
|
597 |
117 |
dgisselq |
printf(" DMAC[%d]: %08x/%08x/%08x(%03x)%d%d%d%d -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
|
598 |
113 |
dgisselq |
m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state,
|
599 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_waddr,
|
600 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_raddr,
|
601 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_len,
|
602 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
|
603 |
117 |
dgisselq |
m_core->v__DOT__zippy__DOT__dma_controller__DOT__last_read_request,
|
604 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__last_read_ack,
|
605 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__last_write_request,
|
606 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__last_write_ack,
|
607 |
113 |
dgisselq |
m_core->v__DOT__zippy__DOT__dc_cyc,
|
608 |
|
|
// m_core->v__DOT__zippy__DOT__dc_stb,
|
609 |
|
|
(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 2)?1:0,
|
610 |
|
|
|
611 |
|
|
((m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 4)
|
612 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 5)
|
613 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
|
614 |
|
|
//(m_core->v__DOT__zippy__DOT__dc_we)?'W':'R',
|
615 |
|
|
(m_core->v__DOT__zippy__DOT__dc_ack)?'A':' ',
|
616 |
|
|
(m_core->v__DOT__zippy__DOT__dc_stall)?'S':' ',
|
617 |
|
|
m_core->v__DOT__zippy__DOT__dc_addr,
|
618 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__rdaddr,
|
619 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nread,
|
620 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nracks,
|
621 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwacks,
|
622 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwritten,
|
623 |
|
|
m_core->v__DOT__zippy__DOT__dc_data);
|
624 |
117 |
dgisselq |
*/
|
625 |
113 |
dgisselq |
|
626 |
117 |
dgisselq |
#ifdef OPT_ZIPSYSTEM
|
627 |
113 |
dgisselq |
printf(" %08x-PIC%08x",
|
628 |
|
|
m_core->v__DOT__zippy__DOT__main_int_vector,
|
629 |
|
|
m_core->v__DOT__zippy__DOT__pic_data);
|
630 |
117 |
dgisselq |
#endif
|
631 |
113 |
dgisselq |
|
632 |
117 |
dgisselq |
printf(" R0 = %08x", m_core->v__DOT__zippy__DOT__thecpu__DOT__regset[0]);
|
633 |
|
|
|
634 |
75 |
dgisselq |
printf("\n"); fflush(stdout);
|
635 |
|
|
} m_last_writeout = writeout;
|
636 |
113 |
dgisselq |
|
637 |
|
|
int writing_to_uart;
|
638 |
|
|
writing_to_uart = (m_core->v__DOT__wb_stb)
|
639 |
|
|
&&(m_core->v__DOT__wb_addr == 0x010b)
|
640 |
|
|
&&(m_core->v__DOT__wb_we);
|
641 |
|
|
if (writing_to_uart) {
|
642 |
|
|
printf("SENT-TO-UART: %02x %c\n",
|
643 |
|
|
(m_core->v__DOT__wb_data & 0x0ff),
|
644 |
|
|
isgraph(m_core->v__DOT__wb_data&0x0ff)
|
645 |
|
|
? m_core->v__DOT__wb_data&0x0ff
|
646 |
|
|
: '.');
|
647 |
|
|
assert((m_core->v__DOT__wb_data & (~0xff))==0);
|
648 |
|
|
}
|
649 |
|
|
#endif // DEBUGGING_OUTPUT
|
650 |
4 |
dgisselq |
}
|
651 |
|
|
|
652 |
117 |
dgisselq |
#ifdef DEBUGGING_OUTPUT
|
653 |
113 |
dgisselq |
bool dcd_ce(void) {
|
654 |
|
|
if (!m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)
|
655 |
|
|
return true;
|
656 |
117 |
dgisselq |
// if (!m_core->v__DOT__zippy__DOT__thecpu__DOT__op_stall)
|
657 |
|
|
// return true;
|
658 |
113 |
dgisselq |
return false;
|
659 |
|
|
}
|
660 |
117 |
dgisselq |
#endif
|
661 |
113 |
dgisselq |
|
662 |
4 |
dgisselq |
};
|
663 |
|
|
|
664 |
|
|
BUSMASTER_TB *tb;
|
665 |
|
|
|
666 |
|
|
void busmaster_kill(int v) {
|
667 |
|
|
tb->kill();
|
668 |
75 |
dgisselq |
fprintf(stderr, "KILLED!!\n");
|
669 |
4 |
dgisselq |
exit(0);
|
670 |
|
|
}
|
671 |
|
|
|
672 |
|
|
int main(int argc, char **argv) {
|
673 |
|
|
Verilated::commandArgs(argc, argv);
|
674 |
|
|
tb = new BUSMASTER_TB;
|
675 |
|
|
|
676 |
|
|
// signal(SIGINT, busmaster_kill);
|
677 |
|
|
|
678 |
|
|
tb->reset();
|
679 |
96 |
dgisselq |
if (argc > 1)
|
680 |
|
|
tb->setsdcard(argv[1]);
|
681 |
|
|
else
|
682 |
|
|
tb->setsdcard("/dev/zero");
|
683 |
4 |
dgisselq |
|
684 |
|
|
while(1)
|
685 |
|
|
tb->tick();
|
686 |
|
|
|
687 |
|
|
exit(0);
|
688 |
|
|
}
|
689 |
|
|
|