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[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 117

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1 46 dgisselq
`define XULA25
2 2 dgisselq
///////////////////////////////////////////////////////////////////////////
3
//
4
// Filename:    busmaster.v
5
//
6
// Project:     XuLA2 board
7
//
8
// Purpose:     This is the highest level, Verilator simulatable, portion of
9
//              the XuLA2 core.  You should be able to successfully Verilate 
10
//      this file, and then build a test bench that tests and proves the
11
//      capability of anything within here.
12
//
13
//      In general, this means the file is little more than a wishbone
14
//      interconnect that connects multiple devices together.  User-JTAG
15
//      commands come in via i_rx_stb and i_rx_data.  These are converted into
16
//      wishbone bus interactions, the results of which come back out via
17
//      o_tx_data and o_tx_stb.
18
//
19
//
20
// Creator:     Dan Gisselquist, Ph.D.
21
//              Gisselquist Technology, LLC
22
//
23
///////////////////////////////////////////////////////////////////////////
24
//
25
// Copyright (C) 2015, Gisselquist Technology, LLC
26
//
27
// This program is free software (firmware): you can redistribute it and/or
28
// modify it under the terms of  the GNU General Public License as published
29
// by the Free Software Foundation, either version 3 of the License, or (at
30
// your option) any later version.
31
//
32
// This program is distributed in the hope that it will be useful, but WITHOUT
33
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
34
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
35
// for more details.
36
//
37
// License:     GPL, v3, as defined and found on www.gnu.org,
38
//              http://www.gnu.org/licenses/gpl.html
39
//
40
//
41
///////////////////////////////////////////////////////////////////////////
42
//
43 31 dgisselq
 
44 46 dgisselq
//
45
// Configuration question #1
46
//
47
//      What innate capabilities are built into the board?
48
//
49 2 dgisselq
`define INCLUDE_ZIPCPU
50 101 dgisselq
 
51
// Without the ZipCPU competing for the bus, we don't need to delay it by a
52
// cycle.
53
`ifndef INCLUDE_ZIPCPU
54
`define NO_ZIP_WBU_DELAY
55
`endif
56
`ifdef  VERILATOR
57
`define NO_ZIP_WBU_DELAY
58
`endif
59
 
60 2 dgisselq
`define IMPLEMENT_ONCHIP_RAM
61 31 dgisselq
`ifndef VERILATOR
62
`ifndef XULA25
63 74 dgisselq
// `define      FANCY_ICAP_ACCESS
64 31 dgisselq
`endif
65
`endif
66 2 dgisselq
`define FLASH_ACCESS
67 74 dgisselq
`ifdef  XULA25
68
`define SDCARD_ACCESS
69
`endif
70 18 dgisselq
//
71 46 dgisselq
 
72
 
73 18 dgisselq
//
74 46 dgisselq
// Configuration question #2
75
//
76
//      Are any scopes built in to the board?
77
//
78
 
79
//
80
// Position #1: The flash scope, or perhaps the wishbone bus/uart/jtag scope
81
//
82 2 dgisselq
// `define      FLASH_SCOPE
83 46 dgisselq
`ifndef FLASH_SCOPE
84
// `define      WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
85
`endif
86
//
87 74 dgisselq
// Position #2: The ICAP configuration scope, could also be the SDCard scope
88
// depending on how we configure ourselves here
89 46 dgisselq
//
90 74 dgisselq
`ifdef  XULA25
91 18 dgisselq
`ifdef  FANCY_ICAP_ACCESS
92 117 dgisselq
// `define      CFG_SCOPE // Only defined if we have the access ...
93 74 dgisselq
`else
94
`ifdef  SDCARD_ACCESS
95 117 dgisselq
// `define      SDCARD_SCOPE
96 18 dgisselq
`endif
97 74 dgisselq
`endif
98
`endif
99 46 dgisselq
//
100 74 dgisselq
// Position #3: The SDRAM scope / UART scope (never both)
101 46 dgisselq
//
102 74 dgisselq
// `define      SDRAM_SCOPE
103
// `define      UART_SCOPE
104 46 dgisselq
//
105
// Position #4: The Zip CPU scope
106
//
107 113 dgisselq
`ifdef  INCLUDE_ZIPCPU
108
`ifdef  VERILATOR
109
`define ZIP_SCOPE
110
`else // VERILATOR
111 31 dgisselq
`ifdef  XULA25
112 117 dgisselq
// `define      ZIP_SCOPE
113 113 dgisselq
`endif // XULA25
114
`endif // VERILATOR
115
`endif // INCLUDE_ZIPCPU
116 31 dgisselq
 
117 2 dgisselq
module  busmaster(i_clk, i_rst,
118
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
119
                // The SPI Flash lines
120
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
121
                // The SDRAM lines
122
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n,
123
                        o_ram_we_n, o_ram_bs, o_ram_addr,
124
                        o_ram_drive_data, i_ram_data, o_ram_data,
125
                        o_ram_dqm,
126
                // Generic GPIO
127
                i_gpio, o_gpio, o_pwm,
128
                i_rx_uart, o_tx_uart);
129
        parameter       ZIP_ADDRESS_WIDTH=24, NGPO=15, NGPI=15,
130
                        ZA=ZIP_ADDRESS_WIDTH;
131
        input                   i_clk, i_rst;
132
        // The bus commander, via an external JTAG port
133
        input                   i_rx_stb;
134
        input           [7:0]    i_rx_data;
135
        output  wire            o_tx_stb;
136
        output  wire    [7:0]    o_tx_data;
137
        input                   i_tx_busy;
138
        // SPI flash control
139
        output  wire            o_sf_cs_n, o_sd_cs_n;
140
        output  wire            o_spi_sck, o_spi_mosi;
141
        input                   i_spi_miso;
142
        // SDRAM control
143
        output  wire            o_ram_cs_n, o_ram_cke;
144
        output  wire            o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
145
        output  wire    [12:0]   o_ram_addr;
146
        output  wire    [1:0]    o_ram_bs;
147
        output  wire            o_ram_drive_data;
148
        input           [15:0]   i_ram_data;
149
        output  wire    [15:0]   o_ram_data;
150
        output  wire    [1:0]    o_ram_dqm;
151
        input   [(NGPI-1):0]     i_gpio;
152
        output wire [(NGPO-1):0] o_gpio;
153
        output  wire            o_pwm;
154
        input                   i_rx_uart;
155
        output  wire            o_tx_uart;
156
 
157
 
158
        //
159
        //
160
        // Master wishbone wires
161
        //
162
        //
163
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
164
        wire    [31:0]   wb_data, wb_idata, wb_addr;
165
 
166
        //
167
        //
168
        // First BUS master source: The JTAG
169
        //
170
        //
171
        wire    [31:0]   dwb_idata;
172
 
173
        // Wires going to devices
174
        wire            wbu_cyc, wbu_stb, wbu_we;
175
        wire    [31:0]   wbu_addr, wbu_data;
176
        // and then coming from devices
177
        wire            wbu_ack, wbu_stall, wbu_err;
178
        wire    [31:0]   wbu_idata;
179
        // And then headed back home
180
        wire    w_interrupt;
181
        // Oh, and the debug control for the ZIP CPU
182
        wire            wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
183 9 dgisselq
        assign  wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
184 2 dgisselq
        wire    [31:0]   zip_dbg_data;
185 101 dgisselq
        wire            wbu_dbg;
186 2 dgisselq
        wbubus  genbus(i_clk, i_rx_stb, i_rx_data,
187
                        wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
188
`ifdef  INCLUDE_ZIPCPU
189
                        ((~wbu_zip_sel)&&(wbu_ack))
190
                                ||((wbu_zip_sel)&&(zip_dbg_ack)),
191
                        ((~wbu_zip_sel)&&(wbu_stall))
192
                                ||((wbu_zip_sel)&&(zip_dbg_stall)),
193
                                wbu_err, (wbu_zip_sel)?zip_dbg_data:dwb_idata,
194
`else
195
                        wbu_ack, wbu_stall,
196
                                wbu_err, dwb_idata,
197
`endif
198
                        w_interrupt,
199 101 dgisselq
                        o_tx_stb, o_tx_data, i_tx_busy,
200
                        wbu_dbg);
201 2 dgisselq
 
202
 
203
        //
204
        //
205
        // Second BUS master source: The ZipCPU
206
        //
207
        //
208
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
209
        wire    [(ZA-1):0]       w_zip_addr;
210
        wire    [31:0]   zip_addr, zip_data;
211
        // and then coming from devices
212
        wire            zip_ack, zip_stall, zip_err;
213
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
214
        wire    [31:0]   dwb_addr, dwb_odata;
215 74 dgisselq
        wire    [8:0]    w_ints_to_zip_cpu;
216 2 dgisselq
`ifdef  INCLUDE_ZIPCPU
217 113 dgisselq
`ifdef  ZIP_SCOPE
218
        wire    [31:0]   zip_debug;
219
`endif
220 31 dgisselq
`ifdef  XULA25
221 113 dgisselq
        zipsystem #(24'h2000,ZA,10,1,9)
222 2 dgisselq
                zippy(i_clk, 1'b0,
223
                        // Zippys wishbone interface
224
                        zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
225
                                zip_ack, zip_stall, dwb_idata, zip_err,
226
                        w_ints_to_zip_cpu, zip_cpu_int,
227
                        // Debug wishbone interface
228
                        ((wbu_cyc)&&(wbu_zip_sel)),
229
                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
230
                                wbu_data,
231 113 dgisselq
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data
232
`ifdef  ZIP_SCOPE
233
                        , zip_debug
234
`endif
235
                        );
236 31 dgisselq
`else
237 117 dgisselq
        zipbones #(24'h2000,ZA,10,1)
238 31 dgisselq
                zippy(i_clk, 1'b0,
239
                        // Zippys wishbone interface
240
                        zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
241
                                zip_ack, zip_stall, dwb_idata, zip_err,
242
                        w_interrupt, zip_cpu_int,
243
                        // Debug wishbone interface
244
                        ((wbu_cyc)&&(wbu_zip_sel)),
245
                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
246
                                wbu_data,
247 113 dgisselq
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data
248
`ifdef  ZIP_SCOPE
249
                                , zip_debug
250 31 dgisselq
`endif
251 113 dgisselq
                );
252
`endif
253 2 dgisselq
        generate
254
        if (ZA < 32)
255
                assign  zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
256
        else
257
                assign  zip_addr = w_zip_addr;
258
        endgenerate
259
 
260
 
261
        //
262
        //
263
        // And an arbiter to decide who gets to access the bus
264
        //
265
        //
266
        /*
267
        wbarbiter #(32,32) wbu_zip_arbiter(i_clk, i_rst,
268
                // The UART interface Master
269
                wbu_addr, wbu_data, wbu_we, (wbu_stb)&&(~wbu_zip_sel),
270
                        (wbu_cyc)&&(~wbu_zip_sel), wbu_ack, wbu_stall, wbu_err,
271
                // The ZIP CPU Master
272
                zip_addr, zip_data, zip_we, zip_stb,
273
                        zip_cyc, zip_ack, zip_stall, zip_err,
274
                // Common bus returns
275
                dwb_addr,dwb_odata,dwb_we,dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err);
276
        */
277
        wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
278
                // The ZIP CPU Master -- gets priority in the arbiter
279
                zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
280
                        zip_ack, zip_stall, zip_err,
281
                // The JTAG interface Master, secondary priority,
282
                // will suffer a 1clk delay in arbitration
283
                (wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
284
                        wbu_addr, wbu_data,
285
                        wbu_ack, wbu_stall, wbu_err,
286
                // Common bus returns
287
                dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
288
                        dwb_ack, dwb_stall, dwb_err);
289
 
290 101 dgisselq
        // 
291
        // 
292
        // And because the ZIP CPU and the Arbiter create an unacceptable
293
        // delay, we fail timing.  So we add in a delay cycle ...
294
        // 
295
        // 
296
`ifdef  NO_ZIP_WBU_DELAY
297
        assign  wb_cyc    = dwb_cyc;
298
        assign  wb_stb    = dwb_stb;
299
        assign  wb_we     = dwb_we;
300
        assign  wb_addr   = dwb_addr;
301
        assign  wb_data   = dwb_odata;
302
        assign  dwb_idata = wb_idata;
303
        assign  dwb_ack   = wb_ack;
304
        assign  dwb_stall = wb_stall;
305
        assign  dwb_err   = wb_err;
306 2 dgisselq
`else
307 101 dgisselq
        busdelay        wbu_zip_delay(i_clk,
308
                        dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
309
                                dwb_ack, dwb_stall, dwb_idata, dwb_err,
310
                        wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
311
                                wb_ack, wb_stall, wb_idata, wb_err);
312
`endif
313
 
314
 
315
`else // if no ZIP_CPU
316 2 dgisselq
        assign  zip_cyc = 1'b0;
317
        assign  zip_stb = 1'b0;
318
        assign  zip_we  = 1'b0;
319
        assign  zip_cpu_int = 1'b0;
320
        assign  zip_addr = 32'h000;
321
        assign  zip_data = 32'h000;
322
 
323
        reg     r_zip_dbg_ack;
324
        initial r_zip_dbg_ack = 1'b0;
325
        always @(posedge i_clk)
326
                r_zip_dbg_ack <= ((wbu_cyc)&&(wbu_zip_sel)&(wbu_stb));
327
        assign  zip_dbg_ack = r_zip_dbg_ack;
328
        assign  zip_dbg_stall = 1'b0;
329
        assign  zip_dbg_data = 32'h000;
330
 
331
        assign  dwb_addr = wbu_addr;
332
        assign  dwb_odata = wbu_data;
333
        assign  dwb_we = wbu_we;
334
        assign  dwb_stb = (wbu_stb);
335
        assign  dwb_cyc = (wbu_cyc);
336 117 dgisselq
        assign  wb_cyc  = dwb_cyc;
337
        assign  wb_stb  = dwb_stb;
338
        assign  wb_we   = dwb_we;
339
        assign  wb_addr = dwb_addr;
340
        assign  wb_data = dwb_odata;
341 2 dgisselq
        assign  wbu_ack = dwb_ack;
342
        assign  wbu_stall = dwb_stall;
343
        assign  dwb_idata = wb_idata;
344
        assign  wbu_err = dwb_err;
345
`endif
346
 
347
 
348
 
349
        wire    io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
350
                        cfg_sel, mem_sel, sdram_sel, sdcard_sel,
351
                        none_sel, many_sel, io_bank;
352
        wire    io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
353
                        sdram_ack, sdcard_ack, uart_ack, pwm_ack;
354
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall,
355
                        sdram_stall, sdcard_stall, uart_stall, pwm_stall;
356
 
357
        wire    [31:0]   io_data, flash_data, scop_data, cfg_data, mem_data,
358
                        sdram_data, sdcard_data, uart_data, pwm_data;
359
        reg     [31:0]   bus_err_addr;
360
 
361
        assign  wb_ack = (wb_cyc)&&((io_ack)||(uart_ack)||(pwm_ack)
362
                                ||(scop_ack)||(cfg_ack)
363
                                ||(mem_ack)||(flash_ack)||(sdram_ack)
364
                                ||(sdcard_ack)
365
                                ||((none_sel)&&(1'b1)));
366
        assign  wb_stall = ((io_sel)&&(io_stall))
367
                        ||((uart_sel)&&(uart_stall))
368
                        ||((pwm_sel)&&(pwm_stall))
369
                        ||((scop_sel)&&(scop_stall))
370
                        ||((cfg_sel)&&(cfg_stall))
371
                        ||((mem_sel)&&(mem_stall))
372
                        ||((sdram_sel)&&(sdram_stall))
373
                        ||((sdcard_sel)&&(sdcard_stall))
374
                        ||((flash_sel||flctl_sel)&&(flash_stall));
375
                        // (none_sel)&&(1'b0)
376
 
377
        /*
378
        assign  wb_idata = (io_ack)?io_data
379
                        : ((scop_ack)?scop_data
380
                        : ((cfg_ack)?cfg_data
381
                        : ((mem_ack)?mem_data
382
                        : ((flash_ack)?flash_data
383
                        : 32'h00))));
384
        */
385
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
386
                        : ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
387
                        : ((cfg_ack) ? cfg_data
388
                        : ((sdram_ack|sdcard_ack)
389
                                        ?((sdram_ack)? sdram_data : sdcard_data)
390
                        : ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
391 113 dgisselq
        assign  wb_err = ((wb_stb)&&(none_sel || many_sel))
392
                                || ((wb_cyc)&&(many_ack));
393 2 dgisselq
 
394
        // Addresses ...
395
        //      0000 xxxx       configuration/control registers
396
        //      001x xxxx       Down-sampler taps       (64 taps, 2 at a time)
397
        //      1xxx xxxx       Up-sampler taps
398
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
399 106 dgisselq
 
400 113 dgisselq
`define SPEEDY_IO
401 106 dgisselq
`ifndef SPEEDY_IO
402
 
403 31 dgisselq
        wire    pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
404 2 dgisselq
        assign  io_bank  = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
405 31 dgisselq
        assign  pre_io   = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
406
        assign  io_sel   = (io_bank)&&(pre_io);
407
        assign  pre_pwm  = (wb_addr[4: 1]== 4'h4);
408
        assign  pwm_sel  = (io_bank)&&(pre_pwm);
409
        assign  pre_uart = (wb_addr[4: 1]== 4'h5)||(wb_addr[4:0]==5'h7);
410
        assign  uart_sel = (io_bank)&&(pre_uart);
411
        assign  pre_flctl= (wb_addr[4: 2]== 3'h3);
412
        assign  flctl_sel= (io_bank)&&(pre_flctl);
413
        assign  pre_scop = (wb_addr[4: 3]== 2'h3);
414
        assign  scop_sel = (io_bank)&&(pre_scop);
415 2 dgisselq
        assign  cfg_sel  =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
416
        // zip_sel is not on the bus at this point
417
        assign  mem_sel  =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
418
        assign  flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
419 74 dgisselq
`ifdef  SDCARD_ACCESS
420
        assign  sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
421
`else
422 2 dgisselq
        assign  sdcard_sel=1'b0;
423 74 dgisselq
`endif
424 2 dgisselq
        assign  sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
425 106 dgisselq
`else
426 113 dgisselq
        wire    [3:0]    iovec;
427
        assign  iovec = { wb_addr[23],wb_addr[18],wb_addr[13],wb_addr[8] };
428 31 dgisselq
 
429 113 dgisselq
        assign  sdram_sel = (iovec[3]);
430
        assign  flash_sel = (iovec[3:2]==2'b01);
431
        assign  mem_sel   = (iovec[3:1]==3'b001);
432
        assign  io_bank   = (iovec[3:0]==4'b0001)&&(wb_addr[7:5]==3'b000);
433
        assign  cfg_sel   = (iovec[3:0]==4'b0001)&&(wb_addr[6]);
434
        assign  sdcard_sel= (iovec[3:0]==4'b0001)&&(wb_addr[6:5]==2'b01);
435
        assign  scop_sel  = (io_bank)&&(wb_addr[7:3]==5'b00011);
436
        assign  io_sel    = (io_bank)&&(wb_addr[7:5]==3'b000)
437
                                &&(wb_addr[4:0] != 5'b00111) // Not UART Ctrl
438
                                &&(wb_addr[3] != 1'b1);//Not PWM/UART/Flash/Scp
439
        assign  flctl_sel = (io_bank)&&(wb_addr[4:2]==3'b011);
440
        assign  pwm_sel   = (io_bank)&&(wb_addr[4:1]==4'b0100);
441 106 dgisselq
        // Note that in the following definition, the UART is given four words
442
        // despite the fact that it can probably only use 3.
443 113 dgisselq
        assign  uart_sel  = (io_bank)&&((wb_addr[4:1]==4'b0101)
444
                                        ||(wb_addr[4:0]==5'b00111));
445 106 dgisselq
 
446
`endif
447
 
448 113 dgisselq
        assign  none_sel =((wb_stb)&&(~
449 31 dgisselq
                        (io_sel
450
                        ||uart_sel
451
                        ||pwm_sel
452
                        ||flctl_sel
453
                        ||scop_sel
454
                        ||cfg_sel
455
                        ||mem_sel
456
                        ||sdram_sel
457
                        ||sdcard_sel
458
                        ||flash_sel)));
459 113 dgisselq
        assign  many_sel =((wb_stb)&&(
460 2 dgisselq
                         {3'h0, io_sel}
461
                        +{3'h0, uart_sel}
462
                        +{3'h0, pwm_sel}
463
                        +{3'h0, flctl_sel}
464
                        +{3'h0, scop_sel}
465
                        +{3'h0, cfg_sel}
466
                        +{3'h0, mem_sel}
467
                        +{3'h0, sdram_sel}
468
                        +{3'h0, sdcard_sel}
469
                        +{3'h0, flash_sel} > 1));
470
 
471
        wire    many_ack;
472
        assign  many_ack =((wb_cyc)&&(
473
                         {3'h0, io_ack}
474
                        +{3'h0, uart_ack}
475
                        +{3'h0, pwm_ack}
476 31 dgisselq
                        // FLCTL acks through the flash, so one less check here
477 2 dgisselq
                        +{3'h0, scop_ack}
478
                        +{3'h0, cfg_ack}
479
                        +{3'h0, mem_ack}
480
                        +{3'h0, sdram_ack}
481
                        +{3'h0, sdcard_ack}
482
                        +{3'h0, flash_ack} > 1));
483
 
484
        always @(posedge i_clk)
485
                if (wb_err)
486
                        bus_err_addr <= wb_addr;
487
 
488 74 dgisselq
        wire            flash_interrupt, sdcard_interrupt, scop_interrupt,
489 2 dgisselq
                        uart_rx_int, uart_tx_int, pwm_int;
490 106 dgisselq
        wire    [(NGPO-1):0]     w_gpio;
491 2 dgisselq
        // The I/O processor, herein called an ioslave
492
        ioslave #(NGPO, NGPI) runio(i_clk,
493
                        wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
494
                                wb_data, io_ack, io_stall, io_data,
495 106 dgisselq
                        i_gpio, w_gpio,
496 2 dgisselq
                        bus_err_addr,
497 74 dgisselq
                        {
498
                        sdcard_interrupt,
499
                        uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
500 31 dgisselq
                                flash_interrupt,
501
`ifdef  XULA25
502
                                zip_cpu_int
503
`else
504
                                1'b0
505
`endif
506
                                },
507 2 dgisselq
                        w_ints_to_zip_cpu,
508
                        w_interrupt);
509
                // 8684
510
                // 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall, 
511
                //      wb_err, ~vga_interrupt, 2'b00, flash_interrupt
512
        //
513
 
514
        //
515
        //      UART device
516
        //
517 74 dgisselq
        wire    [31:0]   uart_debug;
518 2 dgisselq
        uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
519
                        wb_cyc, (wb_stb)&&(uart_sel), wb_we,
520 9 dgisselq
                                        { ~wb_addr[2], wb_addr[0]}, wb_data,
521
                        uart_ack, uart_stall, uart_data,
522 74 dgisselq
                        uart_rx_int, uart_tx_int,
523
                        uart_debug);
524 2 dgisselq
 
525
        //
526
        //      PWM (audio) device
527
        //
528 46 dgisselq
        // The audio rate is given by the number of clock ticks between
529
        // samples.  If we are running at 80 MHz, then divide that by the
530
        // sample rate to get the first parameter for the PWM device.  The
531
        // second parameter is zero or one, indicating whether or not the
532
        // audio rate can be adjusted (1), or whether it is fixed within the
533
        // build (0).
534 83 dgisselq
`ifdef  XULA25
535 113 dgisselq
// `define      FMHACK
536 106 dgisselq
 
537
`ifdef  FMHACK
538
        wbfmtxhack      #(16'd1813)     // 44.1 kHz, user adjustable
539
`else
540 113 dgisselq
        wbpwmaudio      #(16'd1813,1,16)        // 44.1 kHz, user adjustable
541 106 dgisselq
`endif
542
 
543 83 dgisselq
`else
544 101 dgisselq
        wbpwmaudio      #(16'h270f,0,16) //  8   kHz, fixed audio rate
545 83 dgisselq
`endif
546 46 dgisselq
                pwmdev(i_clk,
547 2 dgisselq
                        wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
548
                        wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
549 46 dgisselq
 
550 106 dgisselq
`ifdef  FMHACK
551
        assign  o_gpio = {(NGPO){o_pwm}};
552
`else
553
        assign  o_gpio = w_gpio;
554
`endif
555 2 dgisselq
 
556 106 dgisselq
 
557
 
558 2 dgisselq
        //
559
        //      FLASH MEMORY CONFIGURATION ACCESS
560
        //
561
        wire    flash_cs_n, flash_sck, flash_mosi;
562 74 dgisselq
        wire    spi_user, sdcard_grant, flash_grant;
563 2 dgisselq
`ifdef  FLASH_ACCESS
564
        wbspiflash      flashmem(i_clk,
565
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
566
                        wb_addr[17:0], wb_data,
567
                flash_ack, flash_stall, flash_data,
568
                flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
569 74 dgisselq
                flash_interrupt, flash_grant);
570 2 dgisselq
`else
571
        reg     r_flash_ack;
572
        initial r_flash_ack = 1'b0;
573
        always @(posedge i_clk)
574 113 dgisselq
                r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
575 2 dgisselq
 
576
        assign  flash_ack = r_flash_ack;
577
        assign  flash_stall = 1'b0;
578
        assign  flash_data = 32'h0000;
579
        assign  flash_interrupt = 1'b0;
580
 
581
        assign  flash_cs_n = 1'b1;
582
        assign  flash_sck  = 1'b1;
583
        assign  flash_mosi = 1'b1;
584
`endif
585
 
586 74 dgisselq
        //
587
        //      SDCARD ACCESS
588
        //
589
        wire    sdcard_cs_n, sdcard_sck, sdcard_mosi;
590
        wire    [31:0]   sdspi_scope;
591
`ifdef  SDCARD_ACCESS
592
        sdspi   sdcard_controller(i_clk,
593
                // Wishbone interface
594
                wb_cyc, (wb_stb)&&(sdcard_sel), wb_we, wb_addr[1:0], wb_data,
595
                //      return
596
                        sdcard_ack, sdcard_stall, sdcard_data,
597
                // SPI interface
598
                sdcard_cs_n, sdcard_sck, sdcard_mosi, i_spi_miso,
599
                sdcard_interrupt, sdcard_grant, sdspi_scope);
600
`else
601
        reg     r_sdcard_ack;
602
        initial r_sdcard_ack = 1'b0;
603
        always @(posedge i_clk)
604 113 dgisselq
                r_sdcard_ack <= (wb_stb)&&(sdcard_sel);
605 74 dgisselq
        assign  sdcard_stall = 1'b0;
606
        assign  sdcard_ack = r_sdcard_ack;
607
        assign  sdcard_data = 32'h0000;
608
        assign  sdcard_interrupt= 1'b0;
609
`endif  // SDCARD_ACCESS
610
 
611
 
612 2 dgisselq
`ifdef  FLASH_ACCESS
613
`ifdef  SDCARD_ACCESS
614
        spiarbiter      spichk(i_clk,
615 74 dgisselq
                // Channel zero
616 2 dgisselq
                flash_cs_n, flash_sck, flash_mosi,
617 74 dgisselq
                // Channel one
618 2 dgisselq
                sdcard_cs_n, sdcard_sck, sdcard_mosi,
619 74 dgisselq
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi,
620
                spi_user);
621
        assign  sdcard_grant =  spi_user;
622
        assign  flash_grant  = ~spi_user;
623 2 dgisselq
`else
624
        // Flash access, but no SD card access
625
        assign  o_sf_cs_n  = flash_cs_n;
626
        assign  o_sd_cs_n  = 1'b1;
627
        assign  o_spi_sck  = flash_sck;
628
        assign  o_spi_mosi = flash_mosi;
629 74 dgisselq
        assign  spi_user = 1'b0;
630 83 dgisselq
        assign  flash_grant = 1'b1;
631
        assign  sdcard_grant= 1'b0;
632 2 dgisselq
`endif // SDCARD_ACCESS && FLASH_ACCESS
633
`else // FLASH_ACCESS
634
`ifdef  SDCARD_ACCESS
635
        // SDCard access, but no flash access
636
        assign  o_sf_cs_n  = 1'b1;
637
        assign  o_sd_cs_n  = sdcard_cs_n;
638
        assign  o_spi_sck  = sdcard_sck;
639
        assign  o_spi_mosi = sdcard_mosi;
640 74 dgisselq
        assign  spi_user = 1'b1;
641 83 dgisselq
        assign  flash_grant = 1'b0;
642
        assign  sdcard_grant= 1'b1;
643 2 dgisselq
`else
644
        // No SPI access ...
645
        assign  o_sf_cs_n  = 1'b1;
646
        assign  o_sd_cs_n  = 1'b1;
647
        assign  o_spi_sck  = 1'b1;
648
        assign  o_spi_mosi = 1'b1;
649 74 dgisselq
        assign  spi_user = 1'b0;
650 83 dgisselq
        assign  flash_grant = 1'b0;
651
        assign  sdcard_grant= 1'b0;
652 2 dgisselq
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
653
`endif // !FLASH_ACCESS
654
 
655
 
656
        //
657
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
658
        //
659
        wire    [31:0]   cfg_scope;
660
`ifdef  FANCY_ICAP_ACCESS
661
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
662
                                wb_addr[5:0], wb_data,
663
                                cfg_ack, cfg_stall, cfg_data,
664
                                cfg_scope);
665
`else
666
        assign  cfg_scope = 32'h0000;
667
        reg     r_cfg_ack;
668
        initial r_cfg_ack = 1'b0;
669
        always @(posedge i_clk)
670 113 dgisselq
                r_cfg_ack <= ((cfg_sel)&&(wb_stb)&&(~cfg_stall));
671 2 dgisselq
        assign  cfg_ack = r_cfg_ack;
672
        assign  cfg_stall = 1'b0;
673
        assign  cfg_data = 32'h0000;
674
`endif
675
 
676
 
677
        //
678
        //      RAM MEMORY ACCESS
679
        //
680
`ifdef  IMPLEMENT_ONCHIP_RAM
681
        memdev  #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
682
                        wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
683
`else
684
        reg     r_mem_ack;
685
        always @(posedge i_clk)
686 113 dgisselq
                r_mem_ack = (wb_stb)&&(mem_sel);
687 2 dgisselq
        assign  mem_data = 32'h000;
688
        assign  mem_stall = 1'b0;
689
        assign  mem_ack = r_mem_ack;
690
`endif
691
 
692
 
693
        //
694
        //      SDRAM Memory Access
695
        //
696
        wire    [31:0]   sdram_debug;
697
`ifndef BYPASS_SDRAM_ACCESS
698
        wbsdram sdram(i_clk,
699
                wb_cyc, (wb_stb)&&(sdram_sel),
700
                        wb_we, wb_addr[22:0], wb_data,
701
                        sdram_ack, sdram_stall, sdram_data,
702
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n,
703
                        o_ram_bs, o_ram_addr,
704
                        o_ram_drive_data, i_ram_data, o_ram_data, o_ram_dqm,
705
                sdram_debug);
706
`else
707
        reg     r_sdram_ack;
708
        initial r_sdram_ack = 1'b0;
709
        always @(posedge i_clk)
710 113 dgisselq
                r_sdram_ack <= (wb_stb)&&(sdram_sel);
711 2 dgisselq
        assign  sdram_ack = r_sdram_ack;
712
        assign  sdram_stall = 1'b0;
713
        assign  sdram_data = 32'h0000;
714
 
715
        assign  o_ram_ce_n  = 1'b1;
716
        assign  o_ram_ras_n = 1'b1;
717
        assign  o_ram_cas_n = 1'b1;
718
        assign  o_ram_we_n  = 1'b1;
719
 
720
        assign  sdram_debug = 32'h0000;
721
`endif
722
 
723
        //
724
        //
725
        //      WISHBONE SCOPES
726
        //
727
        //
728
        //
729
        //
730 46 dgisselq
        wire    [31:0]   scop_flash_data;
731
        wire    scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
732
 
733
`ifndef FLASH_ACCESS
734 2 dgisselq
`ifdef  FLASH_SCOPE
735 46 dgisselq
`undef  FLASH_SCOPE // FLASH_SCOPE only makes sense if you have flash access
736
`endif
737
`endif
738
 
739
`ifdef  FLASH_SCOPE
740 2 dgisselq
        reg     [31:0]   r_flash_debug, last_flash_debug;
741
        always @(posedge i_clk)
742
                r_flash_debug <= flash_debug;
743
        always @(posedge i_clk)
744
                last_flash_debug <= r_flash_debug;
745
        wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
746
                // Wishbone interface
747
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
748
                        wb_data,
749
                        scop_flash_ack, scop_flash_stall, scop_flash_data,
750
                scop_flash_interrupt);
751
`else
752 46 dgisselq
`ifdef  WBUS_SCOPE
753
        wbscopc #(5'ha) wbuscope(i_clk, 1'b1, wbus_debug[31], wbus_debug[30:0],
754
                // Wishbone interface
755
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
756
                        wb_data,
757
                        scop_flash_ack, scop_flash_stall, scop_flash_data,
758
                scop_flash_interrupt);
759
`else
760 2 dgisselq
        assign  scop_flash_data = 32'h00;
761
        assign  scop_flash_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
762
        assign scop_flash_stall = 1'b0;
763
        assign scop_flash_interrupt = 1'b0;
764
`endif
765 46 dgisselq
`endif
766 2 dgisselq
 
767
 
768
        wire    [31:0]   scop_cfg_data;
769
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
770
`ifdef  CFG_SCOPE
771
        wire            scop_cfg_trigger;
772 113 dgisselq
        assign  scop_cfg_trigger = (wb_stb)&&(cfg_sel);
773 18 dgisselq
        wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
774 2 dgisselq
                // Wishbone interface
775
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
776
                                wb_we, wb_addr[0], wb_data,
777
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
778
                scop_cfg_interrupt);
779
`else
780 74 dgisselq
`ifdef  SDCARD_SCOPE
781
        wire            scop_sd_trigger, scop_sd_ce;
782 113 dgisselq
        assign  scop_sd_trigger = (wb_stb)&&(sdcard_sel)&&(wb_we);
783 74 dgisselq
        assign  scop_sd_ce = 1'b1; // sdspi_scope[31];
784
        wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
785
                        scop_sd_trigger, sdspi_scope,
786
                // Wishbone interface
787
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
788
                        wb_we, wb_addr[0], wb_data,
789
                scop_cfg_ack, scop_cfg_stall, scop_cfg_data,scop_cfg_interrupt);
790
`else
791 2 dgisselq
        assign  scop_cfg_data = 32'h00;
792
        assign  scop_cfg_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
793
        assign  scop_cfg_stall = 1'b0;
794
        assign  scop_cfg_interrupt = 1'b0;
795
`endif
796 74 dgisselq
`endif
797 2 dgisselq
 
798 74 dgisselq
        wire    [31:0]   scop_two_data;
799
        wire            scop_two_ack, scop_two_stall, scop_two_interrupt;
800 2 dgisselq
`ifdef  SDRAM_SCOPE
801
        wire            sdram_trigger;
802 46 dgisselq
        assign  sdram_trigger = sdram_debug[18]; // sdram_sel;
803 2 dgisselq
 
804 46 dgisselq
        wbscope #(5'hb) sdramscope(i_clk, 1'b1, sdram_trigger,
805 2 dgisselq
                        sdram_debug,
806 46 dgisselq
                        //{ sdram_trigger, wb_data[30:0] },
807 2 dgisselq
                // Wishbone interface
808
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
809
                        wb_data,
810 74 dgisselq
                        scop_two_ack, scop_two_stall, scop_two_data,
811
                scop_two_interrupt);
812 2 dgisselq
`else
813 74 dgisselq
`ifdef  UART_SCOPE
814
        wire            uart_trigger;
815
        assign  uart_trigger = uart_debug[31];
816
 
817
        // wbscopc #(5'ha) uartscope(i_clk,1'b1, uart_trigger, uart_debug[30:0],
818
        wbscope #(5'ha) uartscope(i_clk, 1'b1, uart_trigger, uart_debug[31:0],
819
                // Wishbone interface
820
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
821
                        wb_data,
822
                        scop_two_ack, scop_two_stall, scop_two_data,
823
                scop_two_interrupt);
824
`else
825
        assign  scop_two_data = 32'h00;
826
        assign  scop_two_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
827
        assign  scop_two_stall = 1'b0;
828
        assign  scop_two_interrupt = 1'b0;
829 2 dgisselq
`endif
830 74 dgisselq
`endif
831 2 dgisselq
 
832
        wire    [31:0]   scop_zip_data;
833
        wire            scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
834
`ifdef  ZIP_SCOPE
835 113 dgisselq
        reg             zip_trigger, pre_trigger_a, pre_trigger_b;
836
        always @(posedge i_clk)
837
        begin
838
                pre_trigger_a <= (wb_stb)&&(wb_addr[31:0]==32'h010b);
839
                pre_trigger_b <= (|wb_data[31:8]);
840
                zip_trigger= (pre_trigger_a)&&(pre_trigger_b)||(zip_debug[31]);
841
        end
842 74 dgisselq
        wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
843 2 dgisselq
                        zip_debug,
844
                // Wishbone interface
845
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
846
                        wb_data,
847
                        scop_zip_ack, scop_zip_stall, scop_zip_data,
848
                scop_zip_interrupt);
849
`else
850
        assign  scop_zip_data = 32'h00;
851
        assign  scop_zip_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11);
852
        assign  scop_zip_stall = 1'b0;
853
        assign  scop_zip_interrupt = 1'b0;
854
`endif
855
 
856
 
857
        assign  scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
858 74 dgisselq
                                || scop_two_interrupt || scop_zip_interrupt;
859
        assign  scop_ack   = scop_cfg_ack | scop_flash_ack | scop_two_ack | scop_zip_ack;
860 2 dgisselq
        assign  scop_stall = ((~wb_addr[2])?
861
                                ((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
862 74 dgisselq
                                : ((wb_addr[1])?scop_two_stall:scop_zip_stall));
863 2 dgisselq
        assign  scop_data  = ((scop_cfg_ack)?scop_cfg_data
864
                                : ((scop_flash_ack) ? scop_flash_data
865 74 dgisselq
                                : ((scop_two_ack) ? scop_two_data
866 2 dgisselq
                                : scop_zip_data)));
867
 
868
 
869
endmodule
870
 
871
// 0x8684 interrupts ...???

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