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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: regdefs.cpp
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//
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// Project: XuLA2 board
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//
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// Purpose: To give human readable names to the various registers available
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// internal to the processor on the wishbone bus. This file is
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// primarily used for name to number translation within wbregs.cpp.
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// All names for a given register are equivalent, save only that the
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// register will always be identified by its first name in any output.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <stdlib.h>
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#include <strings.h>
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#include <ctype.h>
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#include "regdefs.h"
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const REGNAME raw_bregs[] = {
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// { R_RESET, "RESET" },
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// { R_STATUS, "STATUS" },
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// { R_CONTROL, "CONTROL" },
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{ R_VERSION, "VERSION" },
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{ R_ICONTROL, "ICONTROL" },
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{ R_ICONTROL, "INT" },
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{ R_ICONTROL, "PIC" },
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{ R_ICONTROL, "INTC" },
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{ R_BUSERR, "BUSERR" },
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{ R_BUSERR, "BUS" },
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{ R_DATE, "DATE" },
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{ R_GPIO, "GPIO" },
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{ R_UART_CTRL, "UARTCTRL" },
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{ R_UART_CTRL, "UART" },
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{ R_PWM_INTERVAL,"PWMI" },
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{ R_PWM_DATA, "PWMDATA" },
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{ R_PWM_DATA, "PWM" },
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{ R_UART_RX, "UART-RX" },
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{ R_UART_RX, "RX" },
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{ R_UART_TX, "UART-TX" },
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{ R_UART_TX, "TX" },
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//
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{ R_SPIF_EREG, "SPIFEREG" },
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{ R_SPIF_EREG, "SPIFE" },
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{ R_SPIF_CREG, "SPIFCONF" },
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{ R_SPIF_CREG, "SPIFC" },
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{ R_SPIF_SREG, "SPIFSTAT" },
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{ R_SPIF_SREG, "SPIFS" },
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{ R_SPIF_IDREG, "SPIFID" },
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{ R_SPIF_IDREG, "SPIFI" },
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//
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{ R_CLOCK, "CLOCK" },
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{ R_CLOCK, "TIME" },
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{ R_TIMER, "TIMER" },
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{ R_STOPWATCH, "STOPWACH" },
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{ R_STOPWATCH, "STOPWATCH" },
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{ R_CKALARM, "CKALARM" },
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{ R_CKALARM, "ALARM" },
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{ R_CKSPEED, "CKSPEED" },
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{ R_TIMEHACK, "TIMEHACK" },
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{ R_TIMEHACK, "HACK" },
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{ R_HACKHI, "HACKHI" },
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{ R_HACKLO, "HACKLO" },
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{ R_TIMEHACK, "HACK" },
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// Scopes are defined and come and go. Be aware, therefore, not all
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// of these scopes may be defined at the same time.
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{ R_QSCOPE, "SCOPE" },
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{ R_QSCOPE, "SCOP" },
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{ R_QSCOPED, "SCOPDATA" },
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{ R_QSCOPED, "SCDATA" },
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{ R_CFGSCOPE, "CFGSCOPE" },
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{ R_CFGSCOPE, "CFGSCOP" },
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{ R_CFGSCOPED, "CFGSCOPD" },
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{ R_CPUSCOPE, "CPUSCOPE" },
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{ R_CPUSCOPE, "CPUSCOP" },
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{ R_CPUSCOPED, "CPUSCOPD" },
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{ R_RAMSCOPE, "MEMSCOPE" },
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{ R_RAMSCOPE, "MEMSCOP" },
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{ R_RAMSCOPED, "MEMSCOPD" },
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{ R_RAMSCOPE, "RAMSCOPE" },
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{ R_RAMSCOPE, "RAMSCOP" },
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{ R_RAMSCOPED, "RAMSCOPD" },
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//
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// For working with the ICAPE interface ... if I can ever get a
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// testing environment suitable to prove that it works.
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//
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{ R_CFG_CRC, "FPGACRC" },
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{ R_CFG_FAR_MAJ, "FPGAFARH" },
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{ R_CFG_FAR_MIN, "FPGAFARL" },
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{ R_CFG_FDRI, "FPGAFDRI" },
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{ R_CFG_FDRO, "FPGAFDRO" },
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{ R_CFG_CMD, "FPGACMD" },
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{ R_CFG_CTL, "FPGACTL" },
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{ R_CFG_MASK, "FPGAMASK" },
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{ R_CFG_STAT, "FPGASTAT" },
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{ R_CFG_LOUT, "FPGALOUT" },
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{ R_CFG_COR1, "FPGACOR1" },
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{ R_CFG_COR2, "FPGACOR2" },
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{ R_CFG_PWRDN, "FPGAPWRDN" },
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{ R_CFG_FLR, "FPGAFLR" },
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{ R_CFG_IDCODE, "FPGAIDCODE" },
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{ R_CFG_CWDT, "FPGACWDT" },
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{ R_CFG_HCOPT, "FPGAHCOPT" },
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{ R_CFG_CSBO, "FPGACSBO" },
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{ R_CFG_GEN1, "FPGAGEN1" },
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{ R_CFG_GEN2, "FPGAGEN2" },
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{ R_CFG_GEN3, "FPGAGEN3" },
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{ R_CFG_GEN4, "FPGAGEN4" },
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{ R_CFG_GEN5, "FPGAGEN5" },
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{ R_CFG_MODE, "FPGAMODE" },
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{ R_CFG_GWE, "FPGAGWE" },
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{ R_CFG_GTS, "FPGAGTS" },
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{ R_CFG_MFWR, "FPGAMFWR" },
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{ R_CFG_CCLK, "FPGACCLK" },
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{ R_CFG_SEU, "FPGASEU" },
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{ R_CFG_EXP, "FPGAEXP" },
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{ R_CFG_RDBK, "FPGARDBK" },
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{ R_CFG_BOOTSTS, "BOOTSTS" },
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{ R_CFG_EYE, "FPGAEYE" },
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{ R_CFG_CBC, "FPGACBC" },
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//
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//
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{ R_ZIPCTRL, "ZIPCTRL" },
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{ R_ZIPCTRL, "ZIPC" },
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{ R_ZIPCTRL, "CPU" },
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{ R_ZIPCTRL, "CPUC" },
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{ R_ZIPDATA, "ZIPDATA" },
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{ R_ZIPDATA, "ZIPD" },
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{ R_ZIPDATA, "CPUD" },
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//
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{ RAMBASE, "MEM" },
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{ SPIFLASH, "FLASH" },
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{ SDRAMBASE, "SDRAM" },
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{ SDRAMBASE, "RAM" }
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};
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#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
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const REGNAME *bregs = raw_bregs;
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const int NREGS = RAW_NREGS;
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unsigned addrdecode(const char *v) {
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if (isalpha(v[0])) {
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for(int i=0; i<NREGS; i++)
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if (strcasecmp(v, bregs[i].m_name)==0)
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return bregs[i].m_addr;
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fprintf(stderr, "Unknown register: %s\n", v);
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exit(-2);
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} else
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return strtoul(v, NULL, 0);
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}
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const char *addrname(const unsigned v) {
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for(int i=0; i<NREGS; i++)
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if (bregs[i].m_addr == v)
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return bregs[i].m_name;
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return NULL;
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}
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