| 1 |
2 |
bsa |
/*******************************************************************************************/
|
| 2 |
|
|
/** **/
|
| 3 |
|
|
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
|
| 4 |
|
|
/** **/
|
| 5 |
|
|
/** alu a input multiplexer module Rev 0.0 07/24/2011 **/
|
| 6 |
|
|
/** **/
|
| 7 |
|
|
/*******************************************************************************************/
|
| 8 |
|
|
module aluamux (adda_in, alua_in, alua_reg, aa_reg_out, bit_mask, daa_out, hl_reg_out,
|
| 9 |
|
|
ii_reg, int_addr, ix_reg, iy_reg, pc_reg, rr_reg, rst_addr);
|
| 10 |
|
|
|
| 11 |
|
|
input [7:0] aa_reg_out; /* a register output */
|
| 12 |
|
|
input [7:0] bit_mask; /* bit mask for bit operations */
|
| 13 |
|
|
input [7:0] daa_out; /* daa constant */
|
| 14 |
|
|
input [7:0] ii_reg; /* i register output */
|
| 15 |
|
|
input [7:0] rr_reg; /* r register output */
|
| 16 |
|
|
input [7:0] rst_addr; /* restart address */
|
| 17 |
|
|
input [15:0] hl_reg_out; /* hl register output */
|
| 18 |
|
|
input [15:0] int_addr; /* interrupt address */
|
| 19 |
|
|
input [15:0] ix_reg; /* ix register output */
|
| 20 |
|
|
input [15:0] iy_reg; /* iy register output */
|
| 21 |
|
|
input [15:0] pc_reg; /* pc register output */
|
| 22 |
|
|
input [`ALUA_IDX:0] alua_reg; /* pipelined alu input a mux control */
|
| 23 |
|
|
output [15:0] adda_in; /* address alu a input bus */
|
| 24 |
|
|
output [15:0] alua_in; /* alu a input bus */
|
| 25 |
|
|
|
| 26 |
|
|
/*****************************************************************************************/
|
| 27 |
|
|
/* */
|
| 28 |
|
|
/* signal declarations */
|
| 29 |
|
|
/* */
|
| 30 |
|
|
/*****************************************************************************************/
|
| 31 |
|
|
reg [15:0] alua_in;
|
| 32 |
|
|
reg [15:0] alua_in_0, alua_in_1, alua_in_2, alua_in_3, alua_in_4, alua_in_5;
|
| 33 |
|
|
reg [15:0] alua_in_6, alua_in_7, alua_in_8, alua_in_9, alua_in_10, alua_in_11;
|
| 34 |
|
|
reg [15:0] alua_in_12, alua_in_13;
|
| 35 |
|
|
|
| 36 |
|
|
wire [15:0] adda_in;
|
| 37 |
|
|
wire [15:0] adda_in_0, adda_in_1, adda_in_2, adda_in_4, adda_in_5, adda_in_12;
|
| 38 |
|
|
wire [15:0] adda_in_13;
|
| 39 |
|
|
|
| 40 |
|
|
/*****************************************************************************************/
|
| 41 |
|
|
/* */
|
| 42 |
|
|
/* alu input a select */
|
| 43 |
|
|
/* */
|
| 44 |
|
|
/*****************************************************************************************/
|
| 45 |
|
|
always @ (alua_reg or aa_reg_out or bit_mask or daa_out or ii_reg or int_addr or
|
| 46 |
|
|
hl_reg_out or ix_reg or iy_reg or pc_reg or rr_reg or rst_addr) begin
|
| 47 |
|
|
alua_in_0 = 16'h0;
|
| 48 |
|
|
alua_in_1 = 16'h0;
|
| 49 |
|
|
alua_in_2 = 16'h0;
|
| 50 |
|
|
alua_in_3 = 16'h0;
|
| 51 |
|
|
alua_in_4 = 16'h0;
|
| 52 |
|
|
alua_in_5 = 16'h0;
|
| 53 |
|
|
alua_in_6 = 16'h0;
|
| 54 |
|
|
alua_in_7 = 16'h0;
|
| 55 |
|
|
alua_in_8 = 16'h0;
|
| 56 |
|
|
alua_in_9 = 16'h0;
|
| 57 |
|
|
alua_in_10 = 16'h0;
|
| 58 |
|
|
alua_in_11 = 16'h0;
|
| 59 |
|
|
alua_in_12 = 16'h0;
|
| 60 |
|
|
alua_in_13 = 16'h0;
|
| 61 |
|
|
if (alua_reg[`AA_ONE]) alua_in_0 = 16'h0001;
|
| 62 |
|
|
if (alua_reg[`AA_M1]) alua_in_1 = 16'hffff;
|
| 63 |
|
|
if (alua_reg[`AA_M2]) alua_in_2 = 16'hfffe;
|
| 64 |
|
|
if (alua_reg[`AA_HL]) alua_in_3 = hl_reg_out;
|
| 65 |
|
|
if (alua_reg[`AA_IX]) alua_in_4 = ix_reg;
|
| 66 |
|
|
if (alua_reg[`AA_IY]) alua_in_5 = iy_reg;
|
| 67 |
|
|
if (alua_reg[`AA_PC]) alua_in_6 = pc_reg;
|
| 68 |
|
|
if (alua_reg[`AA_AA]) alua_in_7 = {8'h00, aa_reg_out};
|
| 69 |
|
|
if (alua_reg[`AA_BIT]) alua_in_8 = {8'h00, bit_mask};
|
| 70 |
|
|
if (alua_reg[`AA_DAA]) alua_in_9 = {8'h00, daa_out};
|
| 71 |
|
|
if (alua_reg[`AA_II]) alua_in_10 = {8'h00, ii_reg};
|
| 72 |
|
|
if (alua_reg[`AA_RR]) alua_in_11 = {8'h00, rr_reg};
|
| 73 |
|
|
if (alua_reg[`AA_INT]) alua_in_12 = int_addr;
|
| 74 |
|
|
if (alua_reg[`AA_RST]) alua_in_13 = {8'h00, rst_addr};
|
| 75 |
|
|
end
|
| 76 |
|
|
|
| 77 |
|
|
always @ (alua_in_0 or alua_in_1 or alua_in_2 or alua_in_3 or alua_in_4 or
|
| 78 |
|
|
alua_in_5 or alua_in_6 or alua_in_7 or alua_in_8 or alua_in_9 or
|
| 79 |
|
|
alua_in_10 or alua_in_11 or alua_in_12 or alua_in_13) begin
|
| 80 |
|
|
alua_in = alua_in_0 | alua_in_1 | alua_in_2 | alua_in_3 | alua_in_4 |
|
| 81 |
|
|
alua_in_5 | alua_in_6 | alua_in_7 | alua_in_8 | alua_in_9 |
|
| 82 |
|
|
alua_in_10 | alua_in_11 | alua_in_12 | alua_in_13;
|
| 83 |
|
|
end
|
| 84 |
|
|
|
| 85 |
|
|
/*****************************************************************************************/
|
| 86 |
|
|
/* */
|
| 87 |
|
|
/* address alu input a select */
|
| 88 |
|
|
/* */
|
| 89 |
|
|
/*****************************************************************************************/
|
| 90 |
|
|
assign adda_in_0 = (alua_reg[`AA_ONE]) ? 16'h0001 : 16'h0000;
|
| 91 |
|
|
assign adda_in_1 = (alua_reg[`AA_M1]) ? 16'hffff : 16'h0000;
|
| 92 |
|
|
assign adda_in_2 = (alua_reg[`AA_M2]) ? 16'hfffe : 16'h0000;
|
| 93 |
|
|
assign adda_in_4 = (alua_reg[`AA_IX]) ? ix_reg : 16'h0000;
|
| 94 |
|
|
assign adda_in_5 = (alua_reg[`AA_IY]) ? iy_reg : 16'h0000;
|
| 95 |
|
|
assign adda_in_12 = (alua_reg[`AA_INT]) ? int_addr : 16'h0000;
|
| 96 |
|
|
assign adda_in_13 = (alua_reg[`AA_RST]) ? {8'h00, rst_addr} : 16'h0000;
|
| 97 |
|
|
|
| 98 |
|
|
assign adda_in = adda_in_0 | adda_in_1 | adda_in_2 | adda_in_4 | adda_in_5 |
|
| 99 |
|
|
adda_in_12 | adda_in_13;
|
| 100 |
|
|
|
| 101 |
|
|
endmodule
|
| 102 |
|
|
|
| 103 |
|
|
|
| 104 |
|
|
|
| 105 |
|
|
|
| 106 |
|
|
|
| 107 |
|
|
|
| 108 |
|
|
|
