Subversion Repositories z80control

//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your

//use of Altera Corporation's design tools, logic functions and other

//software and tools, and its AMPP partner logic functions, and any

//output files any of the foregoing (including device programming or

//simulation files), and any associated documentation or information are

//expressly subject to the terms and conditions of the Altera Program

//License Subscription Agreement or other applicable license agreement,

//including, without limitation, that your use is for the sole purpose

//of programming logic devices manufactured by Altera and sold by Altera

//or its authorized distributors.  Please refer to the applicable

//agreement for further details.

// ============================================================

// File Name: CLK_LOCK.v

// Megafunction Name(s):

//                      altclkctrl

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version

// ************************************************************

//Copyright (C) 1991-2005 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic       

//functions, and any output files any of the foregoing           

//(including device programming or simulation files), and any    

//associated documentation or information are expressly subject  

//to the terms and conditions of the Altera Program License      

//Subscription Agreement, Altera MegaCore Function License       

//Agreement, or other applicable license agreement, including,   

//without limitation, that your use is for the sole purpose of   

//programming logic devices manufactured by Altera and sold by   

//Altera or its authorized distributors.  Please refer to the    

//applicable agreement for further details.

//altclkctrl clock_type="Global Clock" DEVICE_FAMILY="CYCLONE II" clkselect ena inclk outclk

//VERSION_BEGIN 5.0 cbx_altclkbuf 2004:11:30:11:29:52:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END

//synthesis_resources = clkctrl 1 

//synopsys translate_off

`timescale 1 ps / 1 ps

//synopsys translate_on

module  CLK_LOCK_altclkctrl_tb8

        (

        clkselect,

        ena,

        inclk,

        outclk) /* synthesis synthesis_clearbox=1 */;

        input   [1:0]  clkselect;

        input   ena;

        input   [3:0]  inclk;

        output   outclk;

        wire  wire_clkctrl1_outclk;

        cycloneii_clkctrl   clkctrl1

        (

        .clkselect(clkselect),

        .ena(ena),

        .inclk(inclk),

        .outclk(wire_clkctrl1_outclk));

        defparam

                clkctrl1.clock_type = "Global Clock",

                clkctrl1.ena_register_mode = "none",

                clkctrl1.lpm_type = "cycloneii_clkctrl";

        assign

                outclk = wire_clkctrl1_outclk;

endmodule //CLK_LOCK_altclkctrl_tb8

//VALID FILE

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module CLK_LOCK (

        inclk,

        outclk)/* synthesis synthesis_clearbox = 1 */;

        input     inclk;

        output    outclk;

        wire  sub_wire0;

        wire  sub_wire1 = 1'h1;

        wire [2:0] sub_wire4 = 3'h0;

        wire [1:0] sub_wire5 = 2'h0;

        wire  outclk = sub_wire0;

        wire  sub_wire2 = inclk;

        wire [3:0] sub_wire3 = {sub_wire4, sub_wire2};

        CLK_LOCK_altclkctrl_tb8 CLK_LOCK_altclkctrl_tb8_component (

                                .ena (sub_wire1),

                                .inclk (sub_wire3),

                                .clkselect (sub_wire5),

                                .outclk (sub_wire0));

endmodule

// ============================================================

// CNX file retrieval info

// ============================================================

// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"

// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

// Retrieval info: CONSTANT: clock_type STRING "Global Clock"

// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"

// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"

// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0

// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0

// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0

// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0

// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v FALSE FALSE