Subversion Repositories z80control

//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your

//use of Altera Corporation's design tools, logic functions and other

//software and tools, and its AMPP partner logic functions, and any

//output files any of the foregoing (including device programming or

//simulation files), and any associated documentation or information are

//expressly subject to the terms and conditions of the Altera Program

//License Subscription Agreement or other applicable license agreement,

//including, without limitation, that your use is for the sole purpose

//of programming logic devices manufactured by Altera and sold by Altera

//or its authorized distributors.  Please refer to the applicable

//agreement for further details.

// ============================================================

// File Name: CLK_LOCK.v

// Megafunction Name(s):

//                      altclkctrl

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version

// ************************************************************

//Copyright (C) 1991-2006 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic 

//functions, and any output files any of the foregoing 

//(including device programming or simulation files), and any 

//associated documentation or information are expressly subject 

//to the terms and conditions of the Altera Program License 

//Subscription Agreement, Altera MegaCore Function License 

//Agreement, or other applicable license agreement, including, 

//without limitation, that your use is for the sole purpose of 

//programming logic devices manufactured by Altera and sold by 

//Altera or its authorized distributors.  Please refer to the 

//applicable agreement for further details.

module CLK_LOCK (

        inclk,

        outclk)/* synthesis synthesis_clearbox = 1 */;

        input     inclk;

        output    outclk;

endmodule

// ============================================================

// CNX file retrieval info

// ============================================================

// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"

// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

// Retrieval info: CONSTANT: clock_type STRING "Global Clock"

// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"

// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"

// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0

// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0

// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0

// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0

// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf TRUE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v TRUE FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v TRUE FALSE