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tylerapohl |
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// ============================================================
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// File Name: CLK_LOCK.v
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// Megafunction Name(s):
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// altclkctrl
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2006 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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module CLK_LOCK (
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inclk,
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outclk)/* synthesis synthesis_clearbox = 1 */;
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input inclk;
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output outclk;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
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// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
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// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
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// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
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// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
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// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
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// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
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// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v TRUE FALSE
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