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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Flash/] [Flash_Controller.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module Flash_Controller(        //      Control Interface
                                                        oDATA,iDATA,iADDR,iCMD,
                                                        oReady,iStart,iCLK,iRST_n,
                                                        //      Flash Interface
                                                        FL_DQ,FL_ADDR,FL_WE_n,FL_CE_n,FL_OE_n,FL_RST_n);
 
/////////////   Control Interface       ////////////////////////
input [21:0] iADDR;
input [7:0]      iDATA;
input [2:0] iCMD;
input iStart,iCLK,iRST_n;
output reg [7:0] oDATA;
output oReady;
/////////////   Flash Interface ////////////////////////
output reg [21:0] FL_ADDR;
inout [7:0] FL_DQ;
output FL_OE_n,FL_CE_n,FL_WE_n,FL_RST_n;
/////////////   Internal Register       ////////////////////////
reg [21:0] Cont_Finish,CMD_Period;
reg [7:0] mDATA;
reg [10:0] Cont_DIV,WE_CLK_Delay,Start_Delay;
reg [3:0] ST;
reg mCLK,mStart,preStart,pre_mCLK,mACT;
reg mFinish;
reg [2:0] r_CMD;
reg [21:0] r_ADDR;
reg [7:0] r_DATA;
/////////////   Internal Wire   ////////////////////////////
wire WE_CLK;
/////////////////////////////////////////////////////////
 
`include "Flash_Command.h"
 
/////////////   Flash Command Period    ////////////////////
parameter PER_READ              =       1;                      //      160             ns
parameter PER_WRITE     =       5;                      //      800     ns
parameter PER_BLK_ERA   =       160000;         //      25.6    ms
parameter PER_SEC_ERA   =       160000;         //      25.6    ms
parameter PER_CHP_ERA   =       640000;         //      102.4   ms              
parameter PER_ENTRY_ID  =       4;                      //      480             ns
parameter PER_RESET             =       1;                      //      160             ns
//////////////   Flash State Machine    ////////////////////
parameter IDEL          =       0;
parameter P1            =       1;
parameter P2            =       2;
parameter P3            =       3;
parameter P4            =       4;
parameter P5            =       5;
parameter P3_PRG        =       6;
parameter P3_DEV        =       7;
parameter P4_PRG        =       8;
parameter P6_BLK_ERA=   9;
parameter P6_SEC_ERA=   10;
parameter P6_CHP_ERA=   11;
parameter READ          =       12;
parameter RESET         =       13;
////////////////        Clcok Setting   /////////////////////
//parameter CLK_Divide =        4;
parameter CLK_Divide =  8;
//parameter CLK_Divide =        16;
/////////////////////////////////////////////////////////
////    FL_OE_n  ?  Write =     1 : Read   = 0                  /////
////    FL_CE_n  ?  IDEL  = 1 : ACTIVE = 0                      /////
////    FL_RST_n ?  ON    = 1 : RESET  = 0                      /////
assign FL_DQ    = FL_OE_n ? mDATA : 8'bzzzzzzzz ;
assign FL_OE_n  = (ST == READ)  ?       1'b0 : 1'b1 ;
assign FL_CE_n  = (ST == IDEL)  ?       1'b1 : 1'b0 ;
assign FL_WE_n  = (ST == IDEL)  ?       1'b1 :
                                  (ST == READ)  ?       1'b1 : WE_CLK;
assign FL_RST_n = (ST == RESET) ?       1'b0 : 1'b1 ;
assign oReady   = mStart ?      1'b0 : mFinish;
/////////////////////////////////////////////////////////
//////////       Flash State & WE Clock Generator       /////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                Cont_DIV                <=0;
                mCLK                    <=0;
        end
        else
        begin
                Cont_DIV                <=Cont_DIV+1;
                mCLK                    <=Cont_DIV[CLK_Divide>>2];
        end
end
////////////////////////////////////////////////////////
//////////////    WE Clock Generator    ////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        WE_CLK_Delay<=0;
        else
        WE_CLK_Delay<={WE_CLK_Delay[9:0],Cont_DIV[CLK_Divide>>2]};
end
assign  WE_CLK  =       (CLK_Divide == 4)       ?       ~WE_CLK_Delay[3]        :
                                        (CLK_Divide == 8)       ?       ~WE_CLK_Delay[4]        :
                                                                                        ~WE_CLK_Delay[10]       ;
////////////////////////////////////////////////////////
///////////      Input Signal & Data Latch      ////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                mStart                  <=0;
                Start_Delay             <=0;
                preStart                <=0;
                pre_mCLK                <=0;
                mACT                    <=0;
        end
        else
        begin
                ////////        State Active Detect     //////////
                if({pre_mCLK,mCLK}==2'b01)
                mACT<=1;
                else
                mACT<=0;
                pre_mCLK<=mCLK;
                //////////////////////////////////////////
                //////  Input Signal & Data Latch       //////
                if({preStart,iStart}==2'b01)
                begin
                        mStart          <=1'b1;
                        Start_Delay     <=8'h00;
                        r_CMD<=iCMD;
                        r_ADDR<=iADDR;
                        r_DATA<=iDATA;
                end
                else
                begin
                        if(Start_Delay<CLK_Divide)
                        Start_Delay<=Start_Delay+1;
                        else
                        mStart<=1'b0;
                end
                preStart<=iStart;
                //////////////////////////////////////////
        end
end
////////////////////////////////////////////////////////
/////////////   Flash Output Latch      ////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        oDATA<=0;
        else
                if( mACT && (ST==READ))
                oDATA<=FL_DQ;
end
////////////////////////////////////////////////////////
//////////////   Flash State Control    ////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        ST<=IDEL;
        else
        begin
                if(mACT)        //      State Active Flag
                begin
                        if(mStart)
                        begin
                                case(r_CMD)
                                CMD_READ        :       ST<=READ;
                                CMD_WRITE       :       ST<=P1;
                                CMD_BLK_ERA     :       ST<=P1;
                                CMD_SEC_ERA     :       ST<=P1;
                                CMD_CHP_ERA     :       ST<=P1;
                                CMD_ENTRY_ID:   ST<=P1;
                                CMD_RESET       :       ST<=RESET;
                                endcase
                        end
                        else
                        begin
                                case(ST)
                                IDEL:           ST <= IDEL;
                                P1:                     ST <= P2;
                                P2:                     begin
                                                                case(r_CMD)
                                                                CMD_WRITE       :       ST <= P3_PRG;
                                                                CMD_ENTRY_ID:   ST <= P3_DEV;
                                                                default         :       ST <= P3;
                                                                endcase
                                                        end
                                P3:                     ST <= P4;
                                P4:                     ST <= P5;
                                P5:                     begin
                                                                case(r_CMD)
                                                                CMD_BLK_ERA     :       ST <= P6_BLK_ERA;
                                                                CMD_SEC_ERA     :       ST <= P6_SEC_ERA;
                                                                CMD_CHP_ERA     :       ST <= P6_CHP_ERA;
                                                                endcase
                                                        end
                                P3_PRG:         ST <= P4_PRG;
                                P3_DEV:         ST <= IDEL;
                                P4_PRG:         ST <= IDEL;
                                P6_BLK_ERA:     ST <= IDEL;
                                P6_SEC_ERA:     ST <= IDEL;
                                P6_CHP_ERA:     ST <= IDEL;
                                READ:           ST <= IDEL;
                                RESET:          ST <= IDEL;
                                endcase
                        end
                end
        end
end
////////////////////////////////////////////////////////
//////////////   Output Finish Control  ////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                mFinish<=0;
                Cont_Finish<=0;
        end
        else
        begin
                if(mACT)        //      State Active Flag
                begin
                        if(mStart)
                        begin
                                mFinish         <=1'b0;
                                Cont_Finish     <=0;
                        end
                        else
                        begin
                                if(Cont_Finish < CMD_Period)
                                Cont_Finish     <=      Cont_Finish+1;
                                else
                                mFinish         <=      1'b1;
                        end
                end
        end
end
////////////////////////////////////////////////////////        
//////////////   Command Period LUT     ////////////////////
always@(posedge iCLK)
begin
        case(r_CMD)
        CMD_READ        :       CMD_Period      <=      PER_READ-1;
        CMD_WRITE       :       CMD_Period      <=      PER_WRITE-1;
        CMD_BLK_ERA     :       CMD_Period      <=      PER_BLK_ERA-1;
        CMD_SEC_ERA     :       CMD_Period      <=      PER_SEC_ERA-1;
        CMD_CHP_ERA     :       CMD_Period      <=      PER_CHP_ERA-1;
        CMD_ENTRY_ID:   CMD_Period      <=      PER_ENTRY_ID-1;
        CMD_RESET       :       CMD_Period      <=      PER_RESET-1;
        endcase
end
////////////////////////////////////////////////////////
////////////////        Command State LUT       ////////////////
always
begin
        case(ST)
        IDEL:   begin
                                FL_ADDR <= 22'h000000;  mDATA   <= 8'h00;
                        end
        P1:             begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'hAA;
                        end
        P2:             begin
                                FL_ADDR <= 22'h000555;  mDATA   <= 8'h55;
                        end
        P3:             begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'h80;
                end
        P4:             begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'hAA;
                end
        P5:             begin
                                FL_ADDR <= 22'h000555;  mDATA   <= 8'h55;
                end
        P3_PRG: begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'hA0;
                end
        P3_DEV: begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'h90;
                end
        P4_PRG: begin
                                FL_ADDR <= r_ADDR;              mDATA   <= r_DATA;
                end
        P6_BLK_ERA:
                        begin
                                FL_ADDR <= r_ADDR<<12;  mDATA   <= 8'h30;
                end
        P6_SEC_ERA:
                        begin
                                FL_ADDR <= r_ADDR<<16;  mDATA   <= 8'h50;
                end
        P6_CHP_ERA:
                        begin
                                FL_ADDR <= 22'h000AAA;  mDATA   <= 8'h10;
                end
        READ:   begin
                                FL_ADDR <= r_ADDR;              mDATA   <= 8'h00;
                        end
        RESET: begin
                                FL_ADDR <= 22'h000000;  mDATA   <= 8'h00;
                        end
        endcase
end
////////////////////////////////////////////////////////
 
endmodule

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Flash/] [Flash_Controller.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module Flash_Controller( // Control Interface`
14			`oDATA,iDATA,iADDR,iCMD,`
15			`oReady,iStart,iCLK,iRST_n,`
16			`// Flash Interface`
17			`FL_DQ,FL_ADDR,FL_WE_n,FL_CE_n,FL_OE_n,FL_RST_n);`
18
19			`///////////// Control Interface ////////////////////////`
20			`input [21:0] iADDR;`
21			`input [7:0] iDATA;`
22			`input [2:0] iCMD;`
23			`input iStart,iCLK,iRST_n;`
24			`output reg [7:0] oDATA;`
25			`output oReady;`
26			`///////////// Flash Interface ////////////////////////`
27			`output reg [21:0] FL_ADDR;`
28			`inout [7:0] FL_DQ;`
29			`output FL_OE_n,FL_CE_n,FL_WE_n,FL_RST_n;`
30			`///////////// Internal Register ////////////////////////`
31			`reg [21:0] Cont_Finish,CMD_Period;`
32			`reg [7:0] mDATA;`
33			`reg [10:0] Cont_DIV,WE_CLK_Delay,Start_Delay;`
34			`reg [3:0] ST;`
35			`reg mCLK,mStart,preStart,pre_mCLK,mACT;`
36			`reg mFinish;`
37			`reg [2:0] r_CMD;`
38			`reg [21:0] r_ADDR;`
39			`reg [7:0] r_DATA;`
40			`///////////// Internal Wire ////////////////////////////`
41			`wire WE_CLK;`
42			`/////////////////////////////////////////////////////////`
43
44			`include "Flash_Command.h"
45
46			`///////////// Flash Command Period ////////////////////`
47			`parameter PER_READ = 1; // 160 ns`
48			`parameter PER_WRITE = 5; // 800 ns`
49			`parameter PER_BLK_ERA = 160000; // 25.6 ms`
50			`parameter PER_SEC_ERA = 160000; // 25.6 ms`
51			`parameter PER_CHP_ERA = 640000; // 102.4 ms`
52			`parameter PER_ENTRY_ID = 4; // 480 ns`
53			`parameter PER_RESET = 1; // 160 ns`
54			`////////////// Flash State Machine ////////////////////`
55			`parameter IDEL = 0;`
56			`parameter P1 = 1;`
57			`parameter P2 = 2;`
58			`parameter P3 = 3;`
59			`parameter P4 = 4;`
60			`parameter P5 = 5;`
61			`parameter P3_PRG = 6;`
62			`parameter P3_DEV = 7;`
63			`parameter P4_PRG = 8;`
64			`parameter P6_BLK_ERA= 9;`
65			`parameter P6_SEC_ERA= 10;`
66			`parameter P6_CHP_ERA= 11;`
67			`parameter READ = 12;`
68			`parameter RESET = 13;`
69			`//////////////// Clcok Setting /////////////////////`
70			`//parameter CLK_Divide = 4;`
71			`parameter CLK_Divide = 8;`
72			`//parameter CLK_Divide = 16;`
73			`/////////////////////////////////////////////////////////`
74			`//// FL_OE_n ? Write = 1 : Read = 0 /////`
75			`//// FL_CE_n ? IDEL = 1 : ACTIVE = 0 /////`
76			`//// FL_RST_n ? ON = 1 : RESET = 0 /////`
77			`assign FL_DQ = FL_OE_n ? mDATA : 8'bzzzzzzzz ;`
78			`assign FL_OE_n = (ST == READ) ? 1'b0 : 1'b1 ;`
79			`assign FL_CE_n = (ST == IDEL) ? 1'b1 : 1'b0 ;`
80			`assign FL_WE_n = (ST == IDEL) ? 1'b1 :`
81			`(ST == READ) ? 1'b1 : WE_CLK;`
82			`assign FL_RST_n = (ST == RESET) ? 1'b0 : 1'b1 ;`
83			`assign oReady = mStart ? 1'b0 : mFinish;`
84			`/////////////////////////////////////////////////////////`
85			`////////// Flash State & WE Clock Generator /////////`
86			`always@(posedge iCLK or negedge iRST_n)`
87			`begin`
88			`if(!iRST_n)`
89			`begin`
90			`Cont_DIV <=0;`
91			`mCLK <=0;`
92			`end`
93			`else`
94			`begin`
95			`Cont_DIV <=Cont_DIV+1;`
96			`mCLK <=Cont_DIV[CLK_Divide>>2];`
97			`end`
98			`end`
99			`////////////////////////////////////////////////////////`
100			`////////////// WE Clock Generator ////////////////`
101			`always@(posedge iCLK or negedge iRST_n)`
102			`begin`
103			`if(!iRST_n)`
104			`WE_CLK_Delay<=0;`
105			`else`
106			`WE_CLK_Delay<={WE_CLK_Delay[9:0],Cont_DIV[CLK_Divide>>2]};`
107			`end`
108			`assign WE_CLK = (CLK_Divide == 4) ? ~WE_CLK_Delay[3] :`
109			`(CLK_Divide == 8) ? ~WE_CLK_Delay[4] :`
110			`~WE_CLK_Delay[10] ;`
111			`////////////////////////////////////////////////////////`
112			`/////////// Input Signal & Data Latch ////////////////`
113			`always@(posedge iCLK or negedge iRST_n)`
114			`begin`
115			`if(!iRST_n)`
116			`begin`
117			`mStart <=0;`
118			`Start_Delay <=0;`
119			`preStart <=0;`
120			`pre_mCLK <=0;`
121			`mACT <=0;`
122			`end`
123			`else`
124			`begin`
125			`//////// State Active Detect //////////`
126			`if({pre_mCLK,mCLK}==2'b01)`
127			`mACT<=1;`
128			`else`
129			`mACT<=0;`
130			`pre_mCLK<=mCLK;`
131			`//////////////////////////////////////////`
132			`////// Input Signal & Data Latch //////`
133			`if({preStart,iStart}==2'b01)`
134			`begin`
135			`mStart <=1'b1;`
136			`Start_Delay <=8'h00;`
137			`r_CMD<=iCMD;`
138			`r_ADDR<=iADDR;`
139			`r_DATA<=iDATA;`
140			`end`
141			`else`
142			`begin`
143			`if(Start_Delay<CLK_Divide)`
144			`Start_Delay<=Start_Delay+1;`
145			`else`
146			`mStart<=1'b0;`
147			`end`
148			`preStart<=iStart;`
149			`//////////////////////////////////////////`
150			`end`
151			`end`
152			`////////////////////////////////////////////////////////`
153			`///////////// Flash Output Latch ////////////////////`
154			`always@(posedge iCLK or negedge iRST_n)`
155			`begin`
156			`if(!iRST_n)`
157			`oDATA<=0;`
158			`else`
159			`if( mACT && (ST==READ))`
160			`oDATA<=FL_DQ;`
161			`end`
162			`////////////////////////////////////////////////////////`
163			`////////////// Flash State Control ////////////////`
164			`always@(posedge iCLK or negedge iRST_n)`
165			`begin`
166			`if(!iRST_n)`
167			`ST<=IDEL;`
168			`else`
169			`begin`
170			`if(mACT) // State Active Flag`
171			`begin`
172			`if(mStart)`
173			`begin`
174			`case(r_CMD)`
175			`CMD_READ : ST<=READ;`
176			`CMD_WRITE : ST<=P1;`
177			`CMD_BLK_ERA : ST<=P1;`
178			`CMD_SEC_ERA : ST<=P1;`
179			`CMD_CHP_ERA : ST<=P1;`
180			`CMD_ENTRY_ID: ST<=P1;`
181			`CMD_RESET : ST<=RESET;`
182			`endcase`
183			`end`
184			`else`
185			`begin`
186			`case(ST)`
187			`IDEL: ST <= IDEL;`
188			`P1: ST <= P2;`
189			`P2: begin`
190			`case(r_CMD)`
191			`CMD_WRITE : ST <= P3_PRG;`
192			`CMD_ENTRY_ID: ST <= P3_DEV;`
193			`default : ST <= P3;`
194			`endcase`
195			`end`
196			`P3: ST <= P4;`
197			`P4: ST <= P5;`
198			`P5: begin`
199			`case(r_CMD)`
200			`CMD_BLK_ERA : ST <= P6_BLK_ERA;`
201			`CMD_SEC_ERA : ST <= P6_SEC_ERA;`
202			`CMD_CHP_ERA : ST <= P6_CHP_ERA;`
203			`endcase`
204			`end`
205			`P3_PRG: ST <= P4_PRG;`
206			`P3_DEV: ST <= IDEL;`
207			`P4_PRG: ST <= IDEL;`
208			`P6_BLK_ERA: ST <= IDEL;`
209			`P6_SEC_ERA: ST <= IDEL;`
210			`P6_CHP_ERA: ST <= IDEL;`
211			`READ: ST <= IDEL;`
212			`RESET: ST <= IDEL;`
213			`endcase`
214			`end`
215			`end`
216			`end`
217			`end`
218			`////////////////////////////////////////////////////////`
219			`////////////// Output Finish Control ////////////////`
220			`always@(posedge iCLK or negedge iRST_n)`
221			`begin`
222			`if(!iRST_n)`
223			`begin`
224			`mFinish<=0;`
225			`Cont_Finish<=0;`
226			`end`
227			`else`
228			`begin`
229			`if(mACT) // State Active Flag`
230			`begin`
231			`if(mStart)`
232			`begin`
233			`mFinish <=1'b0;`
234			`Cont_Finish <=0;`
235			`end`
236			`else`
237			`begin`
238			`if(Cont_Finish < CMD_Period)`
239			`Cont_Finish <= Cont_Finish+1;`
240			`else`
241			`mFinish <= 1'b1;`
242			`end`
243			`end`
244			`end`
245			`end`
246			`////////////////////////////////////////////////////////`
247			`////////////// Command Period LUT ////////////////////`
248			`always@(posedge iCLK)`
249			`begin`
250			`case(r_CMD)`
251			`CMD_READ : CMD_Period <= PER_READ-1;`
252			`CMD_WRITE : CMD_Period <= PER_WRITE-1;`
253			`CMD_BLK_ERA : CMD_Period <= PER_BLK_ERA-1;`
254			`CMD_SEC_ERA : CMD_Period <= PER_SEC_ERA-1;`
255			`CMD_CHP_ERA : CMD_Period <= PER_CHP_ERA-1;`
256			`CMD_ENTRY_ID: CMD_Period <= PER_ENTRY_ID-1;`
257			`CMD_RESET : CMD_Period <= PER_RESET-1;`
258			`endcase`
259			`end`
260			`////////////////////////////////////////////////////////`
261			`//////////////// Command State LUT ////////////////`
262			`always`
263			`begin`
264			`case(ST)`
265			`IDEL: begin`
266			`FL_ADDR <= 22'h000000; mDATA <= 8'h00;`
267			`end`
268			`P1: begin`
269			`FL_ADDR <= 22'h000AAA; mDATA <= 8'hAA;`
270			`end`
271			`P2: begin`
272			`FL_ADDR <= 22'h000555; mDATA <= 8'h55;`
273			`end`
274			`P3: begin`
275			`FL_ADDR <= 22'h000AAA; mDATA <= 8'h80;`
276			`end`
277			`P4: begin`
278			`FL_ADDR <= 22'h000AAA; mDATA <= 8'hAA;`
279			`end`
280			`P5: begin`
281			`FL_ADDR <= 22'h000555; mDATA <= 8'h55;`
282			`end`
283			`P3_PRG: begin`
284			`FL_ADDR <= 22'h000AAA; mDATA <= 8'hA0;`
285			`end`
286			`P3_DEV: begin`
287			`FL_ADDR <= 22'h000AAA; mDATA <= 8'h90;`
288			`end`
289			`P4_PRG: begin`
290			`FL_ADDR <= r_ADDR; mDATA <= r_DATA;`
291			`end`
292			`P6_BLK_ERA:`
293			`begin`
294			`FL_ADDR <= r_ADDR<<12; mDATA <= 8'h30;`
295			`end`
296			`P6_SEC_ERA:`
297			`begin`
298			`FL_ADDR <= r_ADDR<<16; mDATA <= 8'h50;`
299			`end`
300			`P6_CHP_ERA:`
301			`begin`
302			`FL_ADDR <= 22'h000AAA; mDATA <= 8'h10;`
303			`end`
304			`READ: begin`
305			`FL_ADDR <= r_ADDR; mDATA <= 8'h00;`
306			`end`
307			`RESET: begin`
308			`FL_ADDR <= 22'h000000; mDATA <= 8'h00;`
309			`end`
310			`endcase`
311			`end`
312			`////////////////////////////////////////////////////////`
313
314			`endmodule`