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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Flash/] [Flash_Multiplexer.v] - Blame information for rev 12

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1 12 tylerapohl 
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors.  Please refer to the applicable
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//agreement for further details.
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module Flash_Multiplexer(       //      Host Side
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                                                        oHS_DATA,iHS_DATA,iHS_ADDR,iHS_CMD,oHS_Ready,iHS_Start,
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                                                        //      Async Side 1
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                                                        oAS1_DATA,iAS1_ADDR,
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                                                        //      Async Side 2
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                                                        oAS2_DATA,iAS2_ADDR,
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                                                        //      Async Side 3
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                                                        oAS3_DATA,iAS3_ADDR,
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                                                        //      Flash Side
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                                                        oFL_DATA,iFL_DATA,oFL_ADDR,oFL_CMD,iFL_Ready,oFL_Start,
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                                                        //      Control Signals
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                                                        iSelect,iCLK,iRST_n);
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//      Host Side
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input   [21:0]   iHS_ADDR;
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input   [7:0]    iHS_DATA;
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input   [2:0]    iHS_CMD;
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input                   iHS_Start;
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output  [7:0]    oHS_DATA;
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output                  oHS_Ready;
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//      Async Side 1
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input   [21:0]   iAS1_ADDR;
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output  [7:0]    oAS1_DATA;
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//      Async Side 2
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input   [21:0]   iAS2_ADDR;
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output  [7:0]    oAS2_DATA;
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//      Async Side 3
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input   [21:0]   iAS3_ADDR;
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output  [7:0]    oAS3_DATA;
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//      Flash Side
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input   [7:0]    iFL_DATA;
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input                   iFL_Ready;
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output  [21:0]   oFL_ADDR;
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output  [7:0]    oFL_DATA;
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output  [2:0]    oFL_CMD;
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output                  oFL_Start;
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//      Control Signals
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input   [1:0]    iSelect;
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input                   iCLK;
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input                   iRST_n;
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//      Internal Register
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reg             [7:0]    mFL_DATA;
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reg             [1:0]    ST;
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reg                             mFL_Start;
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//      Host Side Select
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assign  oHS_DATA        =       (iSelect==0)     ?       iFL_DATA        :       8'h00   ;
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assign  oHS_Ready       =       (iSelect==0)     ?       iFL_Ready       :       1'b1    ;
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//      ASync Side
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assign  oAS1_DATA       =       (iSelect==1)    ?       mFL_DATA        :       8'h00   ;
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assign  oAS2_DATA       =       (iSelect==2)    ?       mFL_DATA        :       8'h00   ;
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assign  oAS3_DATA       =       (iSelect==3)    ?       mFL_DATA        :       8'h00   ;
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//      Flash Side
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assign  oFL_DATA        =       (iSelect==0)     ?       iHS_DATA        :       8'hFF   ;
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assign  oFL_ADDR        =       (iSelect==0)     ?       iHS_ADDR        :
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                                                (iSelect==1)    ?       iAS1_ADDR       :
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                                                (iSelect==2)    ?       iAS2_ADDR       :
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                                                                                        iAS3_ADDR       ;
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assign  oFL_CMD         =       (iSelect==0)     ?       iHS_CMD         :       3'b000  ;
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assign  oFL_Start       =       (iSelect==0)     ?       iHS_Start       :       mFL_Start;
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//      mFL_Start Control & Flash Data Lock
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always@(posedge iCLK or negedge iRST_n)
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begin
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        if(!iRST_n)
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        begin
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                mFL_DATA        <=0;
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                mFL_Start       <=0;
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                ST                      <=0;
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        end
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        else
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        begin
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                if(iSelect!=0)
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                begin
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                        case(ST)
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                        0:       begin
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                                        mFL_Start<=1;
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                                        ST<=1;
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                                end
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                        1:      begin
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                                        if(iFL_Ready)
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                                        begin
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                                                mFL_DATA<=iFL_DATA;
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                                                mFL_Start<=0;
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                                                ST<=2;
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                                        end
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                                end
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                        2:      ST<=3;
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                        3:      ST<=0;
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                        endcase
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                end
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                else
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                begin
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                        mFL_Start<=0;
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                        ST<=0;
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                end
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        end
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end
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endmodule
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