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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [Sdram_Multiplexer.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module Sdram_Multiplexer        (       //      Host Side
                                                        oHS_DATA,iHS_DATA,iHS_ADDR,iHS_RD,iHS_WR,oHS_Done,
                                                        //      Async Side 1
                                                        oAS1_DATA,iAS1_DATA,iAS1_ADDR,iAS1_WR_n,
                                                        //      Async Side 2
                                                        oAS2_DATA,iAS2_DATA,iAS2_ADDR,iAS2_WR_n,
                                                        //      Async Side 3
                                                        oAS3_DATA,iAS3_DATA,iAS3_ADDR,iAS3_WR_n,
                                                        //      SDRAM Side
                                                        oSDR_DATA,iSDR_DATA,oSDR_ADDR,oSDR_RD,oSDR_WR,iSDR_Done,
                                                        //      Control Signals
                                                        iSelect,iCLK,iRST_n     );
//      Host Side
input   [21:0]   iHS_ADDR;
input   [15:0]   iHS_DATA;
input                   iHS_RD;
input                   iHS_WR;
output  [15:0]   oHS_DATA;
output                  oHS_Done;
//      Async Side 1
input   [21:0]   iAS1_ADDR;
input   [15:0]   iAS1_DATA;
input                   iAS1_WR_n;
output  [15:0]   oAS1_DATA;
//      Async Side 2
input   [21:0]   iAS2_ADDR;
input   [15:0]   iAS2_DATA;
input                   iAS2_WR_n;
output  [15:0]   oAS2_DATA;
//      Async Side 3
input   [21:0]   iAS3_ADDR;
input   [15:0]   iAS3_DATA;
input                   iAS3_WR_n;
output  [15:0]   oAS3_DATA;
//      SDRAM Side
input   [15:0]   iSDR_DATA;
input                   iSDR_Done;
output  [21:0]   oSDR_ADDR;
output  [15:0]   oSDR_DATA;
output                  oSDR_RD;
output                  oSDR_WR;
//      Control Signals
input   [1:0]    iSelect;
input                   iCLK;
input                   iRST_n;
//      Internal Register
reg             [15:0]   mSDR_DATA;
reg             [1:0]    ST;
reg                             mSDR_RD;
reg                             mSDR_WR;
wire                    mAS_WR_n;
 
 
//      Host Side Select
assign  oHS_DATA        =       (iSelect==0)     ?       iSDR_DATA       :       16'h0000;
assign  oHS_Done        =       (iSelect==0)     ?       iSDR_Done       :       1'b1    ;
//      ASync Side
assign  oAS1_DATA       =       (iSelect==1)    ?       mSDR_DATA       :       16'h0000;
assign  oAS2_DATA       =       (iSelect==2)    ?       mSDR_DATA       :       16'h0000;
assign  oAS3_DATA       =       (iSelect==3)    ?       mSDR_DATA       :       16'h0000;
//      SDRAM Side
assign  oSDR_DATA       =       (iSelect==0)     ?       iHS_DATA        :
                                                (iSelect==1)    ?       iAS1_DATA       :
                                                (iSelect==2)    ?       iAS2_DATA       :
                                                                                        iAS3_DATA       ;
assign  oSDR_ADDR       =       (iSelect==0)     ?       iHS_ADDR        :
                                                (iSelect==1)    ?       iAS1_ADDR       :
                                                (iSelect==2)    ?       iAS2_ADDR       :
                                                                                        iAS3_ADDR       ;
assign  oSDR_RD         =       (iSelect==0)     ?       iHS_RD          :       mSDR_RD ;
assign  oSDR_WR         =       (iSelect==0)     ?       iHS_WR          :       mSDR_WR ;
//      Internal Async Write/Read Select
assign  mAS_WR_n        =       (iSelect==0)     ?       1'b0            :
                                                (iSelect==1)    ?       iAS1_WR_n       :
                                                (iSelect==2)    ?       iAS2_WR_n       :
                                                                                        iAS3_WR_n       ;
 
//      Async Control & SDRAM Data Lock
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                mSDR_DATA<=0;
                mSDR_RD<=0;
                mSDR_WR<=0;
                ST<=0;
        end
        else
        begin
                if(iSelect!=0)
                begin
                        case(ST)
                        0:       begin
                                        if(mAS_WR_n)
                                        begin
                                                mSDR_RD<=0;
                                                mSDR_WR<=1;
                                        end
                                        else
                                        begin
                                                mSDR_RD<=1;
                                                mSDR_WR<=0;
                                        end
                                        ST<=1;
                                end
                        1:      begin
                                        if(iSDR_Done)
                                        begin
                                                mSDR_DATA<=iSDR_DATA;
                                                mSDR_RD<=0;
                                                mSDR_WR<=0;
                                                ST<=2;
                                        end
                                end
                        2:      ST<=3;
                        3:      ST<=0;
                        endcase
                end
                else
                begin
                        mSDR_RD<=0;
                        mSDR_WR<=0;
                        ST<=0;
                end
        end
end
endmodule

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module Sdram_Multiplexer ( // Host Side`
14			`oHS_DATA,iHS_DATA,iHS_ADDR,iHS_RD,iHS_WR,oHS_Done,`
15			`// Async Side 1`
16			`oAS1_DATA,iAS1_DATA,iAS1_ADDR,iAS1_WR_n,`
17			`// Async Side 2`
18			`oAS2_DATA,iAS2_DATA,iAS2_ADDR,iAS2_WR_n,`
19			`// Async Side 3`
20			`oAS3_DATA,iAS3_DATA,iAS3_ADDR,iAS3_WR_n,`
21			`// SDRAM Side`
22			`oSDR_DATA,iSDR_DATA,oSDR_ADDR,oSDR_RD,oSDR_WR,iSDR_Done,`
23			`// Control Signals`
24			`iSelect,iCLK,iRST_n );`
25			`// Host Side`
26			`input [21:0] iHS_ADDR;`
27			`input [15:0] iHS_DATA;`
28			`input iHS_RD;`
29			`input iHS_WR;`
30			`output [15:0] oHS_DATA;`
31			`output oHS_Done;`
32			`// Async Side 1`
33			`input [21:0] iAS1_ADDR;`
34			`input [15:0] iAS1_DATA;`
35			`input iAS1_WR_n;`
36			`output [15:0] oAS1_DATA;`
37			`// Async Side 2`
38			`input [21:0] iAS2_ADDR;`
39			`input [15:0] iAS2_DATA;`
40			`input iAS2_WR_n;`
41			`output [15:0] oAS2_DATA;`
42			`// Async Side 3`
43			`input [21:0] iAS3_ADDR;`
44			`input [15:0] iAS3_DATA;`
45			`input iAS3_WR_n;`
46			`output [15:0] oAS3_DATA;`
47			`// SDRAM Side`
48			`input [15:0] iSDR_DATA;`
49			`input iSDR_Done;`
50			`output [21:0] oSDR_ADDR;`
51			`output [15:0] oSDR_DATA;`
52			`output oSDR_RD;`
53			`output oSDR_WR;`
54			`// Control Signals`
55			`input [1:0] iSelect;`
56			`input iCLK;`
57			`input iRST_n;`
58			`// Internal Register`
59			`reg [15:0] mSDR_DATA;`
60			`reg [1:0] ST;`
61			`reg mSDR_RD;`
62			`reg mSDR_WR;`
63			`wire mAS_WR_n;`
64
65
66			`// Host Side Select`
67			`assign oHS_DATA = (iSelect==0) ? iSDR_DATA : 16'h0000;`
68			`assign oHS_Done = (iSelect==0) ? iSDR_Done : 1'b1 ;`
69			`// ASync Side`
70			`assign oAS1_DATA = (iSelect==1) ? mSDR_DATA : 16'h0000;`
71			`assign oAS2_DATA = (iSelect==2) ? mSDR_DATA : 16'h0000;`
72			`assign oAS3_DATA = (iSelect==3) ? mSDR_DATA : 16'h0000;`
73			`// SDRAM Side`
74			`assign oSDR_DATA = (iSelect==0) ? iHS_DATA :`
75			`(iSelect==1) ? iAS1_DATA :`
76			`(iSelect==2) ? iAS2_DATA :`
77			`iAS3_DATA ;`
78			`assign oSDR_ADDR = (iSelect==0) ? iHS_ADDR :`
79			`(iSelect==1) ? iAS1_ADDR :`
80			`(iSelect==2) ? iAS2_ADDR :`
81			`iAS3_ADDR ;`
82			`assign oSDR_RD = (iSelect==0) ? iHS_RD : mSDR_RD ;`
83			`assign oSDR_WR = (iSelect==0) ? iHS_WR : mSDR_WR ;`
84			`// Internal Async Write/Read Select`
85			`assign mAS_WR_n = (iSelect==0) ? 1'b0 :`
86			`(iSelect==1) ? iAS1_WR_n :`
87			`(iSelect==2) ? iAS2_WR_n :`
88			`iAS3_WR_n ;`
89
90			`// Async Control & SDRAM Data Lock`
91			`always@(posedge iCLK or negedge iRST_n)`
92			`begin`
93			`if(!iRST_n)`
94			`begin`
95			`mSDR_DATA<=0;`
96			`mSDR_RD<=0;`
97			`mSDR_WR<=0;`
98			`ST<=0;`
99			`end`
100			`else`
101			`begin`
102			`if(iSelect!=0)`
103			`begin`
104			`case(ST)`
105			`0: begin`
106			`if(mAS_WR_n)`
107			`begin`
108			`mSDR_RD<=0;`
109			`mSDR_WR<=1;`
110			`end`
111			`else`
112			`begin`
113			`mSDR_RD<=1;`
114			`mSDR_WR<=0;`
115			`end`
116			`ST<=1;`
117			`end`
118			`1: begin`
119			`if(iSDR_Done)`
120			`begin`
121			`mSDR_DATA<=iSDR_DATA;`
122			`mSDR_RD<=0;`
123			`mSDR_WR<=0;`
124			`ST<=2;`
125			`end`
126			`end`
127			`2: ST<=3;`
128			`3: ST<=0;`
129			`endcase`
130			`end`
131			`else`
132			`begin`
133			`mSDR_RD<=0;`
134			`mSDR_WR<=0;`
135			`ST<=0;`
136			`end`
137			`end`
138			`end`
139			`endmodule`

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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [Sdram_Multiplexer.v] - Blame information for rev 12