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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [control_interface.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module control_interface(
        CLK,
        RESET_N,
        CMD,
        ADDR,
        REF_ACK,
                INIT_ACK,
        CM_ACK,
        NOP,
        READA,
        WRITEA,
        REFRESH,
        PRECHARGE,
        LOAD_MODE,
        SADDR,
        REF_REQ,
                INIT_REQ,
        CMD_ACK
        );
 
`include        "Sdram_Params.h"
 
input                           CLK;                    // System Clock
input                           RESET_N;                // System Reset
input   [2:0]                   CMD;                    // Command input
input   [`ASIZE-1:0]            ADDR;                   // Address
input                           REF_ACK;                // Refresh request acknowledge
input                                                   INIT_ACK;                               // Initial request acknowledge
input                           CM_ACK;                 // Command acknowledge
output                          NOP;                    // Decoded NOP command
output                          READA;                  // Decoded READA command
output                          WRITEA;                 // Decoded WRITEA command
output                          REFRESH;                // Decoded REFRESH command
output                          PRECHARGE;              // Decoded PRECHARGE command
output                          LOAD_MODE;              // Decoded LOAD_MODE command
output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
output                          REF_REQ;                // Hidden refresh request
output                          INIT_REQ;               // Hidden initial request
output                          CMD_ACK;                // Command acknowledge
 
 
 
reg                             NOP;
reg                             READA;
reg                             WRITEA;
reg                             REFRESH;
reg                             PRECHARGE;
reg                             LOAD_MODE;
reg     [`ASIZE-1:0]            SADDR;
reg                             REF_REQ;
reg                             INIT_REQ;
reg                             CMD_ACK;
 
// Internal signals
reg     [15:0]                  timer;
reg             [15:0]                                   init_timer;
 
 
 
// Command decode and ADDR register
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)
        begin
                NOP             <= 0;
                READA           <= 0;
                WRITEA          <= 0;
                SADDR           <= 0;
        end
 
        else
        begin
 
                SADDR <= ADDR;                                  // register the address to keep proper
                                                                // alignment with the command
 
                if (CMD == 3'b000)                              // NOP command
                        NOP <= 1;
                else
                        NOP <= 0;
 
                if (CMD == 3'b001)                              // READA command
                        READA <= 1;
                else
                        READA <= 0;
 
                if (CMD == 3'b010)                              // WRITEA command
                        WRITEA <= 1;
                else
                        WRITEA <= 0;
 
        end
end
 
 
//  Generate CMD_ACK
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)
                CMD_ACK <= 0;
        else
                if ((CM_ACK == 1) & (CMD_ACK == 0))
                        CMD_ACK <= 1;
                else
                        CMD_ACK <= 0;
end
 
 
// refresh timer
always @(posedge CLK or negedge RESET_N) begin
        if (RESET_N == 0)
        begin
                timer           <= 0;
                REF_REQ         <= 0;
        end
        else
        begin
                if (REF_ACK == 1)
                                begin
                        timer <= REF_PER;
                                        REF_REQ <=0;
                                end
                                else if (INIT_REQ == 1)
                                begin
                        timer <= REF_PER+200;
                                        REF_REQ <=0;
                                end
                else
                        timer <= timer - 1'b1;
 
                if (timer==0)
                    REF_REQ    <= 1;
 
        end
end
 
// initial timer
always @(posedge CLK or negedge RESET_N) begin
        if (RESET_N == 0)
        begin
                init_timer      <= 0;
                                REFRESH         <= 0;
                PRECHARGE       <= 0;
                                LOAD_MODE               <= 0;
                                INIT_REQ                <= 0;
        end
        else
        begin
                if (init_timer < (INIT_PER+201))
                                        init_timer      <= init_timer+1;
 
                                if (init_timer < INIT_PER)
                                begin
                                        REFRESH         <=0;
                                        PRECHARGE       <=0;
                                        LOAD_MODE       <=0;
                                        INIT_REQ        <=1;
                                end
                                else if(init_timer == (INIT_PER+20))
                                begin
                                        REFRESH         <=0;
                                        PRECHARGE       <=1;
                                        LOAD_MODE       <=0;
                                        INIT_REQ        <=0;
                                end
                                else if(        (init_timer == (INIT_PER+40))   ||
                                                        (init_timer == (INIT_PER+60))   ||
                                                        (init_timer == (INIT_PER+80))   ||
                                                        (init_timer == (INIT_PER+100))  ||
                                                        (init_timer == (INIT_PER+120))  ||
                                                        (init_timer == (INIT_PER+140))  ||
                                                        (init_timer == (INIT_PER+160))  ||
                                                        (init_timer == (INIT_PER+180))  )
                                begin
                                        REFRESH         <=1;
                                        PRECHARGE       <=0;
                                        LOAD_MODE       <=0;
                                        INIT_REQ        <=0;
                                end
                                else if(init_timer == (INIT_PER+200))
                                begin
                                        REFRESH         <=0;
                                        PRECHARGE       <=0;
                                        LOAD_MODE       <=1;
                                        INIT_REQ        <=0;
                                end
                                else
                                begin
                                        REFRESH         <=0;
                                        PRECHARGE       <=0;
                                        LOAD_MODE       <=0;
                                        INIT_REQ        <=0;
                                end
        end
end
 
endmodule
 

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [control_interface.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module control_interface(`
14			`CLK,`
15			`RESET_N,`
16			`CMD,`
17			`ADDR,`
18			`REF_ACK,`
19			`INIT_ACK,`
20			`CM_ACK,`
21			`NOP,`
22			`READA,`
23			`WRITEA,`
24			`REFRESH,`
25			`PRECHARGE,`
26			`LOAD_MODE,`
27			`SADDR,`
28			`REF_REQ,`
29			`INIT_REQ,`
30			`CMD_ACK`
31			`);`
32
33			`include "Sdram_Params.h"
34
35			`input CLK; // System Clock`
36			`input RESET_N; // System Reset`
37			`input [2:0] CMD; // Command input`
38			input [`ASIZE-1:0] ADDR; // Address
39			`input REF_ACK; // Refresh request acknowledge`
40			`input INIT_ACK; // Initial request acknowledge`
41			`input CM_ACK; // Command acknowledge`
42			`output NOP; // Decoded NOP command`
43			`output READA; // Decoded READA command`
44			`output WRITEA; // Decoded WRITEA command`
45			`output REFRESH; // Decoded REFRESH command`
46			`output PRECHARGE; // Decoded PRECHARGE command`
47			`output LOAD_MODE; // Decoded LOAD_MODE command`
48			output [`ASIZE-1:0] SADDR; // Registered version of ADDR
49			`output REF_REQ; // Hidden refresh request`
50			`output INIT_REQ; // Hidden initial request`
51			`output CMD_ACK; // Command acknowledge`
52
53
54
55			`reg NOP;`
56			`reg READA;`
57			`reg WRITEA;`
58			`reg REFRESH;`
59			`reg PRECHARGE;`
60			`reg LOAD_MODE;`
61			reg [`ASIZE-1:0] SADDR;
62			`reg REF_REQ;`
63			`reg INIT_REQ;`
64			`reg CMD_ACK;`
65
66			`// Internal signals`
67			`reg [15:0] timer;`
68			`reg [15:0] init_timer;`
69
70
71
72			`// Command decode and ADDR register`
73			`always @(posedge CLK or negedge RESET_N)`
74			`begin`
75			`if (RESET_N == 0)`
76			`begin`
77			`NOP <= 0;`
78			`READA <= 0;`
79			`WRITEA <= 0;`
80			`SADDR <= 0;`
81			`end`
82
83			`else`
84			`begin`
85
86			`SADDR <= ADDR; // register the address to keep proper`
87			`// alignment with the command`
88
89			`if (CMD == 3'b000) // NOP command`
90			`NOP <= 1;`
91			`else`
92			`NOP <= 0;`
93
94			`if (CMD == 3'b001) // READA command`
95			`READA <= 1;`
96			`else`
97			`READA <= 0;`
98
99			`if (CMD == 3'b010) // WRITEA command`
100			`WRITEA <= 1;`
101			`else`
102			`WRITEA <= 0;`
103
104			`end`
105			`end`
106
107
108			`// Generate CMD_ACK`
109			`always @(posedge CLK or negedge RESET_N)`
110			`begin`
111			`if (RESET_N == 0)`
112			`CMD_ACK <= 0;`
113			`else`
114			`if ((CM_ACK == 1) & (CMD_ACK == 0))`
115			`CMD_ACK <= 1;`
116			`else`
117			`CMD_ACK <= 0;`
118			`end`
119
120
121			`// refresh timer`
122			`always @(posedge CLK or negedge RESET_N) begin`
123			`if (RESET_N == 0)`
124			`begin`
125			`timer <= 0;`
126			`REF_REQ <= 0;`
127			`end`
128			`else`
129			`begin`
130			`if (REF_ACK == 1)`
131			`begin`
132			`timer <= REF_PER;`
133			`REF_REQ <=0;`
134			`end`
135			`else if (INIT_REQ == 1)`
136			`begin`
137			`timer <= REF_PER+200;`
138			`REF_REQ <=0;`
139			`end`
140			`else`
141			`timer <= timer - 1'b1;`
142
143			`if (timer==0)`
144			`REF_REQ <= 1;`
145
146			`end`
147			`end`
148
149			`// initial timer`
150			`always @(posedge CLK or negedge RESET_N) begin`
151			`if (RESET_N == 0)`
152			`begin`
153			`init_timer <= 0;`
154			`REFRESH <= 0;`
155			`PRECHARGE <= 0;`
156			`LOAD_MODE <= 0;`
157			`INIT_REQ <= 0;`
158			`end`
159			`else`
160			`begin`
161			`if (init_timer < (INIT_PER+201))`
162			`init_timer <= init_timer+1;`
163
164			`if (init_timer < INIT_PER)`
165			`begin`
166			`REFRESH <=0;`
167			`PRECHARGE <=0;`
168			`LOAD_MODE <=0;`
169			`INIT_REQ <=1;`
170			`end`
171			`else if(init_timer == (INIT_PER+20))`
172			`begin`
173			`REFRESH <=0;`
174			`PRECHARGE <=1;`
175			`LOAD_MODE <=0;`
176			`INIT_REQ <=0;`
177			`end`
178			`else if( (init_timer == (INIT_PER+40)) \|\|`
179			`(init_timer == (INIT_PER+60)) \|\|`
180			`(init_timer == (INIT_PER+80)) \|\|`
181			`(init_timer == (INIT_PER+100)) \|\|`
182			`(init_timer == (INIT_PER+120)) \|\|`
183			`(init_timer == (INIT_PER+140)) \|\|`
184			`(init_timer == (INIT_PER+160)) \|\|`
185			`(init_timer == (INIT_PER+180)) )`
186			`begin`
187			`REFRESH <=1;`
188			`PRECHARGE <=0;`
189			`LOAD_MODE <=0;`
190			`INIT_REQ <=0;`
191			`end`
192			`else if(init_timer == (INIT_PER+200))`
193			`begin`
194			`REFRESH <=0;`
195			`PRECHARGE <=0;`
196			`LOAD_MODE <=1;`
197			`INIT_REQ <=0;`
198			`end`
199			`else`
200			`begin`
201			`REFRESH <=0;`
202			`PRECHARGE <=0;`
203			`LOAD_MODE <=0;`
204			`INIT_REQ <=0;`
205			`end`
206			`end`
207			`end`
208
209			`endmodule`
210