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https://opencores.org/ocsvn/z80control/z80control/trunk
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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module SEG7_LUT_4 ( oSEG0,oSEG1,oSEG2,oSEG3,iDIG );
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input [15:0] iDIG;
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output [6:0] oSEG0,oSEG1,oSEG2,oSEG3;
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SEG7_LUT u0 ( oSEG0,iDIG[3:0] );
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SEG7_LUT u1 ( oSEG1,iDIG[7:4] );
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SEG7_LUT u2 ( oSEG2,iDIG[11:8] );
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SEG7_LUT u3 ( oSEG3,iDIG[15:12] );
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endmodule
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