URL https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk

Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [layout/] [tcl/] [vgsim.tcl] - Blame information for rev 7

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open_project ./project_n1.xpr
 
config_webtalk -user off
 
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
 
open_run impl_1
write_verilog -force -mode timesim -sdf_anno true -sdf_file project_n1.sdf project_n1_impl_timing.v
#write_verilog -force -mode timesim -sdf_file project_n1.sdf project_n1_impl_timing.v
write_sdf project_n1.sdf
 
close_project

Line No.	Rev	Author	Line
1	7	kuzmi4
2			`open_project ./project_n1.xpr`
3
4			`config_webtalk -user off`
5
6			`update_compile_order -fileset sources_1`
7			`update_compile_order -fileset sim_1`
8
9			`open_run impl_1`
10			`write_verilog -force -mode timesim -sdf_anno true -sdf_file project_n1.sdf project_n1_impl_timing.v`
11			`#write_verilog -force -mode timesim -sdf_file project_n1.sdf project_n1_impl_timing.v`
12			`write_sdf project_n1.sdf`
13
14			`close_project`

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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [layout/] [tcl/] [vgsim.tcl] - Blame information for rev 7