| 1 |
6 |
gdevic |
// Automatically generated by genref.py
|
| 2 |
|
|
|
| 3 |
|
|
// Module: control/decode_state.v
|
| 4 |
|
|
output logic ctl_state_iy_set,
|
| 5 |
|
|
output logic ctl_state_ixiy_clr,
|
| 6 |
|
|
output logic ctl_state_ixiy_we,
|
| 7 |
|
|
output logic ctl_state_halt_set,
|
| 8 |
|
|
output logic ctl_state_tbl_clr,
|
| 9 |
|
|
output logic ctl_state_tbl_ed_set,
|
| 10 |
|
|
output logic ctl_state_tbl_cb_set,
|
| 11 |
|
|
output logic ctl_state_alu,
|
| 12 |
|
|
output logic ctl_repeat_we,
|
| 13 |
|
|
|
| 14 |
|
|
// Module: control/interrupts.v
|
| 15 |
|
|
output logic ctl_iff1_iff2,
|
| 16 |
|
|
output logic ctl_iffx_we,
|
| 17 |
|
|
output logic ctl_iffx_bit,
|
| 18 |
|
|
output logic ctl_im_we,
|
| 19 |
|
|
output logic ctl_no_ints,
|
| 20 |
|
|
|
| 21 |
|
|
// Module: control/ir.v
|
| 22 |
|
|
output logic ctl_ir_we,
|
| 23 |
|
|
|
| 24 |
|
|
// Module: control/memory_ifc.v
|
| 25 |
|
|
output logic ctl_mRead,
|
| 26 |
|
|
output logic ctl_mWrite,
|
| 27 |
|
|
output logic ctl_iorw,
|
| 28 |
|
|
|
| 29 |
|
|
// Module: alu/alu_control.v
|
| 30 |
|
|
output logic ctl_shift_en,
|
| 31 |
|
|
output logic ctl_daa_oe,
|
| 32 |
|
|
output logic ctl_alu_op_low,
|
| 33 |
|
|
output logic ctl_cond_short,
|
| 34 |
|
|
output logic ctl_alu_core_hf,
|
| 35 |
|
|
output logic ctl_eval_cond,
|
| 36 |
|
|
output logic ctl_66_oe,
|
| 37 |
|
|
output logic [1:0] ctl_pf_sel,
|
| 38 |
|
|
|
| 39 |
|
|
// Module: alu/alu_select.v
|
| 40 |
|
|
output logic ctl_alu_oe,
|
| 41 |
|
|
output logic ctl_alu_shift_oe,
|
| 42 |
|
|
output logic ctl_alu_op2_oe,
|
| 43 |
|
|
output logic ctl_alu_res_oe,
|
| 44 |
|
|
output logic ctl_alu_op1_oe,
|
| 45 |
|
|
output logic ctl_alu_bs_oe,
|
| 46 |
|
|
output logic ctl_alu_op1_sel_bus,
|
| 47 |
|
|
output logic ctl_alu_op1_sel_low,
|
| 48 |
|
|
output logic ctl_alu_op1_sel_zero,
|
| 49 |
|
|
output logic ctl_alu_op2_sel_zero,
|
| 50 |
|
|
output logic ctl_alu_op2_sel_bus,
|
| 51 |
|
|
output logic ctl_alu_op2_sel_lq,
|
| 52 |
|
|
output logic ctl_alu_sel_op2_neg,
|
| 53 |
|
|
output logic ctl_alu_sel_op2_high,
|
| 54 |
|
|
output logic ctl_alu_core_R,
|
| 55 |
|
|
output logic ctl_alu_core_V,
|
| 56 |
|
|
output logic ctl_alu_core_S,
|
| 57 |
|
|
|
| 58 |
|
|
// Module: alu/alu_flags.v
|
| 59 |
|
|
output logic ctl_flags_oe,
|
| 60 |
|
|
output logic ctl_flags_bus,
|
| 61 |
|
|
output logic ctl_flags_alu,
|
| 62 |
|
|
output logic ctl_flags_nf_set,
|
| 63 |
|
|
output logic ctl_flags_cf_set,
|
| 64 |
|
|
output logic ctl_flags_cf_cpl,
|
| 65 |
|
|
output logic ctl_flags_cf_we,
|
| 66 |
|
|
output logic ctl_flags_sz_we,
|
| 67 |
|
|
output logic ctl_flags_xy_we,
|
| 68 |
|
|
output logic ctl_flags_hf_we,
|
| 69 |
|
|
output logic ctl_flags_pf_we,
|
| 70 |
|
|
output logic ctl_flags_nf_we,
|
| 71 |
|
|
output logic ctl_flags_cf2_we,
|
| 72 |
|
|
output logic ctl_flags_hf_cpl,
|
| 73 |
|
|
output logic ctl_flags_use_cf2,
|
| 74 |
|
|
output logic ctl_flags_hf2_we,
|
| 75 |
|
|
output logic ctl_flags_nf_clr,
|
| 76 |
|
|
output logic ctl_alu_zero_16bit,
|
| 77 |
|
|
output logic [1:0] ctl_flags_cf2_sel,
|
| 78 |
|
|
|
| 79 |
|
|
// Module: registers/reg_file.v
|
| 80 |
|
|
output logic ctl_sw_4d,
|
| 81 |
|
|
output logic ctl_sw_4u,
|
| 82 |
|
|
output logic ctl_reg_in_hi,
|
| 83 |
|
|
output logic ctl_reg_in_lo,
|
| 84 |
|
|
output logic ctl_reg_out_lo,
|
| 85 |
|
|
output logic ctl_reg_out_hi,
|
| 86 |
|
|
|
| 87 |
|
|
// Module: registers/reg_control.v
|
| 88 |
|
|
output logic ctl_reg_exx,
|
| 89 |
|
|
output logic ctl_reg_ex_af,
|
| 90 |
|
|
output logic ctl_reg_ex_de_hl,
|
| 91 |
|
|
output logic ctl_reg_use_sp,
|
| 92 |
|
|
output logic ctl_reg_sel_pc,
|
| 93 |
|
|
output logic ctl_reg_sel_ir,
|
| 94 |
|
|
output logic ctl_reg_sel_wz,
|
| 95 |
|
|
output logic ctl_reg_gp_we,
|
| 96 |
|
|
output logic ctl_reg_not_pc,
|
| 97 |
|
|
output logic ctl_reg_sys_we_lo,
|
| 98 |
|
|
output logic ctl_reg_sys_we_hi,
|
| 99 |
|
|
output logic ctl_reg_sys_we,
|
| 100 |
|
|
output logic [1:0] ctl_reg_gp_hilo,
|
| 101 |
|
|
output logic [1:0] ctl_reg_gp_sel,
|
| 102 |
|
|
output logic [1:0] ctl_reg_sys_hilo,
|
| 103 |
|
|
|
| 104 |
|
|
// Module: bus/address_latch.v
|
| 105 |
|
|
output logic ctl_inc_cy,
|
| 106 |
|
|
output logic ctl_inc_dec,
|
| 107 |
|
|
output logic ctl_inc_zero,
|
| 108 |
|
|
output logic ctl_al_we,
|
| 109 |
|
|
output logic ctl_inc_limit6,
|
| 110 |
|
|
output logic ctl_bus_inc_oe,
|
| 111 |
|
|
output logic ctl_apin_mux,
|
| 112 |
|
|
output logic ctl_apin_mux2,
|
| 113 |
|
|
|
| 114 |
|
|
// Module: bus/bus_control.v
|
| 115 |
|
|
output logic ctl_bus_ff_oe,
|
| 116 |
|
|
output logic ctl_bus_zero_oe,
|
| 117 |
|
|
output logic ctl_bus_db_oe,
|
| 118 |
|
|
|
| 119 |
|
|
// Module: bus/bus_switch.sv
|
| 120 |
|
|
output logic ctl_sw_1u,
|
| 121 |
|
|
output logic ctl_sw_1d,
|
| 122 |
|
|
output logic ctl_sw_2u,
|
| 123 |
|
|
output logic ctl_sw_2d,
|
| 124 |
|
|
output logic ctl_sw_mask543_en,
|
| 125 |
|
|
|
| 126 |
|
|
// Module: bus/data_pins.v
|
| 127 |
|
|
output logic ctl_bus_db_we,
|
