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//---------------------------------------------------------------------------------------
//      Project:                        High Throughput & Low Area AES Core 
//
//      File name:                      tb_kat.v                        (Jan 1, 2011)
//
//      Writer:                         Moti Litochevski 
//
//      Description:
//              This file contains a basic test bench to demonstrate the core functionality & 
//              interfaces including pipelined operation. For each key length the test bench 
//              encrypts four plain text vectors using a single key and then decrypts the four 
//              cipher text vectors using the same key. 
//              The test bench demonstrates the key expansion, encryption and decryption for all 
//              three key lengths with pipelined operation. 
//
//      Revision History:
//
//      Rev <revnumber>                 <Date>                  <owner> 
//              <comment>
// 
//---------------------------------------------------------------------------------------
 
`timescale 1ns / 10ps
module test ();
 
//---------------------------------------------------------------------------------------
// global signals 
reg clock;
reg reset;
 
// test bench variables 
integer dout_count;
 
// UUT interface signals 
reg key_start;
reg enable;
reg enc_dec;
reg [255:0] key_in;
reg [1:0] key_mode;
reg [127:0] data_in;
reg data_in_valid;
wire ready_out;
wire [127:0] data_out;
wire data_out_valid;
wire key_ready;
 
//---------------------------------------------------------------------------------------
// test bench implementation 
// global clock generator 
initial         clock = 1'b1;
always          #10 clock = ~clock;
 
// gloabl reset generator 
initial
begin
        reset = 1'b1;
        #100;
        reset = 1'b0;
end
 
// cosmetics 
initial
begin
        // announce start of simulation 
        $display("");
        $display("-------------------------------------");
        $display("        AES_HT_LA Simulation");
        $display("-------------------------------------");
        $display("");
 
        // VCD dump 
        $dumpfile("test.vcd");
        $dumpvars(0, test);
        $display("");
end
 
// main test bench process control 
initial
begin
        // default input values 
        key_start = 1'b0;
        enable = 1'b1;
        enc_dec = 1'b0;
        key_in = 256'b0;
        key_mode = 2'b0;
        data_in = 128'b0;
        data_in_valid = 1'b0;
        dout_count = 0;
 
        // wait for reset release 
        @(posedge clock);
        wait (~reset);
        @(posedge clock);
 
        // encryption for 128 bit key mode 
        $display("Testing encryption for 128 bit key:");
        $display("-------------------------------------");
        // set core mode to encryption and key size to 128 
        enc_dec <= 1'b0;
        key_mode <= 2'b00;
        // set the key value and start  key expansion 
        key_in[255:128] <= 128'h2b7e151628aed2a6abf7158809cf4f3c;
        key_start <= 1'b1;
        @(posedge clock);
        key_start <= 1'b0;
        @(posedge clock);
        // display key value 
        $display("Key: 128'h%32h", key_in[255:128]);
        // wait for key expansion to finish 
        while (!key_ready) @(posedge clock);
        // announce key expansion ended 
        $display("Key expansion done");
        $display("");
 
        // first plain text input data 
        data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 1: 128'h%32h", data_in);
        // second plain text input data 
        data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 2: 128'h%32h", data_in);
        // third plain text input data 
        data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 3: 128'h%32h", data_in);
        // forth plain text input data 
        data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
        @(posedge clock);
 
        // announce state 
        $display("");
        $display("Waiting for cipher text data");
 
        // wait for all output cipher text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // continue with decryption of the same cipher text without key expansion 
        $display("Testing decryption for 128 bit key:");
        $display("-------------------------------------");
        // set core mode to decryption 
        enc_dec <= 1'b1;
        @(posedge clock);
        // display key value 
        $display("Key: 128'h%32h", key_in[255:128]);
        // announce key expansion is not done again 
        $display("Using the same key, expansion is not required.");
        $display("");
 
        // first cipher text input data 
        data_in[127:0] <= 128'hef0bc156ed8ff21223f247b3e0318a99;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 1: 128'h%32h", data_in);
        // second cipher text input data 
        data_in[127:0] <= 128'hf91914cd01924b124c2ec316b4b35a79;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 2: 128'h%32h", data_in);
        // third cipher text input data 
        data_in[127:0] <= 128'h8df4e9aac5c7573a27d8d055d6e4d64b;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 3: 128'h%32h", data_in);
        // forth cipher text input data 
        data_in[127:0] <= 128'hec8ce641087165a463d4118dc35f9001;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
 
        // announce state 
        $display("");
        $display("Waiting for plain text data");
 
        // wait for all output plain text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // encryption for 192 bit key mode 
        $display("Testing encryption for 192 bit key:");
        $display("-------------------------------------");
        // set core mode to encryption and key size to 192 
        enc_dec <= 1'b0;
        key_mode <= 2'b01;
        // set the key value and start  key expansion 
        key_in[255:64] <= 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;
        key_start <= 1'b1;
        @(posedge clock);
        key_start <= 1'b0;
        @(posedge clock);
        // display key value 
        $display("Key: 192'h%32h", key_in[255:64]);
        // wait for key expansion to finish 
        while (!key_ready) @(posedge clock);
        // announce key expansion ended 
        $display("Key expansion done");
        $display("");
 
        // first plain text input data 
        data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 1: 128'h%32h", data_in);
        // second plain text input data 
        data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 2: 128'h%32h", data_in);
        // third plain text input data 
        data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 3: 128'h%32h", data_in);
        // forth plain text input data 
        data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
        @(posedge clock);
 
        // announce state 
        $display("");
        $display("Waiting for cipher text data");
 
        // wait for all output cipher text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // continue with decryption of the same cipher text without key expansion 
        $display("Testing decryption for 192 bit key:");
        $display("-------------------------------------");
        // set core mode to decryption 
        enc_dec <= 1'b1;
        @(posedge clock);
        // display key value 
        $display("Key: 192'h%32h", key_in[255:64]);
        // announce key expansion is not done again 
        $display("Using the same key, expansion is not required.");
        $display("");
 
        // first cipher text input data 
        data_in[127:0] <= 128'h17d3cbb6a98f64ccd134e0d0b7695aa9;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 1: 128'h%32h", data_in);
        // second cipher text input data 
        data_in[127:0] <= 128'h4a7d86377de2a8faf00f8ef97c2eb982;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 2: 128'h%32h", data_in);
        // third cipher text input data 
        data_in[127:0] <= 128'heb1b03f2acb64bcf28c9991cc8a4fa50;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 3: 128'h%32h", data_in);
        // forth cipher text input data 
        data_in[127:0] <= 128'h2adc503e1c9b669de6b5bc904035547d;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
 
        // announce state 
        $display("");
        $display("Waiting for plain text data");
 
        // wait for all output plain text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // encryption for 256 bit key mode 
        $display("Testing encryption for 256 bit key:");
        $display("-------------------------------------");
        // set core mode to encryption and key size to 256 
        enc_dec <= 1'b0;
        key_mode <= 2'b10;
        // set the key value and start  key expansion 
        key_in[255:0] <= 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
        key_start <= 1'b1;
        @(posedge clock);
        key_start <= 1'b0;
        @(posedge clock);
        // display key value 
        $display("Key: 256'h%32h", key_in[255:64]);
        // wait for key expansion to finish 
        while (!key_ready) @(posedge clock);
        // announce key expansion ended 
        $display("Key expansion done");
        $display("");
 
        // first plain text input data 
        data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 1: 128'h%32h", data_in);
        // second plain text input data 
        data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 2: 128'h%32h", data_in);
        // third plain text input data 
        data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 3: 128'h%32h", data_in);
        // forth plain text input data 
        data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Plaintext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
        @(posedge clock);
 
        // announce state 
        $display("");
        $display("Waiting for cipher text data");
 
        // wait for all output cipher text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // continue with decryption of the same cipher text without key expansion 
        $display("Testing decryption for 256 bit key:");
        $display("-------------------------------------");
        // set core mode to decryption 
        enc_dec <= 1'b1;
        @(posedge clock);
        // display key value 
        $display("Key: 256'h%32h", key_in[255:0]);
        // announce key expansion is not done again 
        $display("Using the same key, expansion is not required.");
        $display("");
 
        // first cipher text input data 
        data_in[127:0] <= 128'h32573d9003bfd345029779298be53b96;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 1: 128'h%32h", data_in);
        // second cipher text input data 
        data_in[127:0] <= 128'ha5f464b57512d05db2bae8d2415b921d;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 2: 128'h%32h", data_in);
        // third cipher text input data 
        data_in[127:0] <= 128'hd83414223d20a0c928b136c884d07ea2;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 3: 128'h%32h", data_in);
        // forth cipher text input data 
        data_in[127:0] <= 128'hc1f968d2a6859137bd9ad9111ad7f6dc;
        data_in_valid <= 1'b1;
        @ (posedge clock);
        // display data value 
        $display("Ciphertext Data 4: 128'h%32h", data_in);
        // no more data can be given to the core 
        data_in_valid <= 1'b0;
 
        // announce state 
        $display("");
        $display("Waiting for plain text data");
 
        // wait for all output plain text data 
        dout_count = 0;
        while (dout_count < 4)
        begin
                // check for a new output data 
                if (data_out_valid)
                        dout_count <= dout_count + 1;
                // wait for next clock cycle 
                @(posedge clock);
        end
        $display("");
 
        // announce simulation end 
        $display("   Simulation Done !!!");
 
        repeat (10) @(posedge clock);
        $finish;
end
 
// unit under test 
aes dut
(
        .clk(clock),
        .reset(reset),
        .i_start(key_start),
        .i_enable(enable),
        .i_ende(enc_dec),
        .i_key(key_in),
        .i_key_mode(key_mode),
        .i_data(data_in),
        .i_data_valid(data_in_valid),
        .o_ready(ready_out),
        .o_data(data_out),
        .o_data_valid(data_out_valid),
        .o_key_ready(key_ready)
);
 
// display output data from the core 
always @ (posedge clock)
   if (data_out_valid)
      $display("Output Data %1d: 128'h%16h", dout_count+1, data_out);
 
endmodule
//---------------------------------------------------------------------------------------
//                                              Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	8	motilito	`//---------------------------------------------------------------------------------------`
2			`// Project: High Throughput & Low Area AES Core`
3			`//`
4			`// File name: tb_kat.v (Jan 1, 2011)`
5			`//`
6			`// Writer: Moti Litochevski`
7			`//`
8			`// Description:`
9			`// This file contains a basic test bench to demonstrate the core functionality &`
10			`// interfaces including pipelined operation. For each key length the test bench`
11			`// encrypts four plain text vectors using a single key and then decrypts the four`
12			`// cipher text vectors using the same key.`
13			`// The test bench demonstrates the key expansion, encryption and decryption for all`
14			`// three key lengths with pipelined operation.`
15			`//`
16			`// Revision History:`
17			`//`
18			`// Rev <revnumber> <Date> <owner>`
19			`// <comment>`
20			`//`
21			`//---------------------------------------------------------------------------------------`
22
23	6	motilito	`timescale 1ns / 10ps
24	8	motilito	`module test ();`
25	6	motilito
26	8	motilito	`//---------------------------------------------------------------------------------------`
27			`// global signals`
28			`reg clock;`
29	7	motilito	`reg reset;`
30	6	motilito
31	8	motilito	`// test bench variables`
32			`integer dout_count;`
33
34			`// UUT interface signals`
35	6	motilito	`reg key_start;`
36	8	motilito	`reg enable;`
37			`reg enc_dec;`
38			`reg [255:0] key_in;`
39			`reg [1:0] key_mode;`
40			`reg [127:0] data_in;`
41			`reg data_in_valid;`
42			`wire ready_out;`
43			`wire [127:0] data_out;`
44			`wire data_out_valid;`
45			`wire key_ready;`
46
47			`//---------------------------------------------------------------------------------------`
48			`// test bench implementation`
49			`// global clock generator`
50			`initial clock = 1'b1;`
51			`always #10 clock = ~clock;`
52
53			`// gloabl reset generator`
54			`initial`
55			`begin`
56	7	motilito	`reset = 1'b1;`
57	6	motilito	`#100;`
58	7	motilito	`reset = 1'b0;`
59	8	motilito	`end`
60
61			`// cosmetics`
62			`initial`
63			`begin`
64			`// announce start of simulation`
65			`$display("");`
66			`$display("-------------------------------------");`
67			`$display(" AES_HT_LA Simulation");`
68			`$display("-------------------------------------");`
69			`$display("");`
70
71			`// VCD dump`
72			`$dumpfile("test.vcd");`
73			`$dumpvars(0, test);`
74			`$display("");`
75			`end`
76
77			`// main test bench process control`
78			`initial`
79			`begin`
80			`// default input values`
81			`key_start = 1'b0;`
82			`enable = 1'b1;`
83			`enc_dec = 1'b0;`
84			`key_in = 256'b0;`
85			`key_mode = 2'b0;`
86			`data_in = 128'b0;`
87			`data_in_valid = 1'b0;`
88			`dout_count = 0;`
89
90			`// wait for reset release`
91			`@(posedge clock);`
92			`wait (~reset);`
93			`@(posedge clock);`
94
95			`// encryption for 128 bit key mode`
96			`$display("Testing encryption for 128 bit key:");`
97			`$display("-------------------------------------");`
98			`// set core mode to encryption and key size to 128`
99			`enc_dec <= 1'b0;`
100			`key_mode <= 2'b00;`
101			`// set the key value and start key expansion`
102			`key_in[255:128] <= 128'h2b7e151628aed2a6abf7158809cf4f3c;`
103	6	motilito	`key_start <= 1'b1;`
104	8	motilito	`@(posedge clock);`
105	6	motilito	`key_start <= 1'b0;`
106	8	motilito	`@(posedge clock);`
107			`// display key value`
108			`$display("Key: 128'h%32h", key_in[255:128]);`
109			`// wait for key expansion to finish`
110			`while (!key_ready) @(posedge clock);`
111			`// announce key expansion ended`
112			`$display("Key expansion done");`
113			`$display("");`
114
115			`// first plain text input data`
116			`data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;`
117			`data_in_valid <= 1'b1;`
118			`@ (posedge clock);`
119			`// display data value`
120			`$display("Plaintext Data 1: 128'h%32h", data_in);`
121			`// second plain text input data`
122			`data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;`
123			`data_in_valid <= 1'b1;`
124			`@ (posedge clock);`
125			`// display data value`
126			`$display("Plaintext Data 2: 128'h%32h", data_in);`
127			`// third plain text input data`
128			`data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;`
129			`data_in_valid <= 1'b1;`
130			`@ (posedge clock);`
131			`// display data value`
132			`$display("Plaintext Data 3: 128'h%32h", data_in);`
133			`// forth plain text input data`
134			`data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;`
135			`data_in_valid <= 1'b1;`
136			`@ (posedge clock);`
137			`// display data value`
138			`$display("Plaintext Data 4: 128'h%32h", data_in);`
139			`// no more data can be given to the core`
140	6	motilito	`data_in_valid <= 1'b0;`
141	8	motilito	`@(posedge clock);`
142
143			`// announce state`
144			`$display("");`
145			`$display("Waiting for cipher text data");`
146
147			`// wait for all output cipher text data`
148			`dout_count = 0;`
149			`while (dout_count < 4)`
150			`begin`
151			`// check for a new output data`
152			`if (data_out_valid)`
153			`dout_count <= dout_count + 1;`
154			`// wait for next clock cycle`
155			`@(posedge clock);`
156			`end`
157			`$display("");`
158
159			`// continue with decryption of the same cipher text without key expansion`
160			`$display("Testing decryption for 128 bit key:");`
161			`$display("-------------------------------------");`
162			`// set core mode to decryption`
163			`enc_dec <= 1'b1;`
164			`@(posedge clock);`
165			`// display key value`
166			`$display("Key: 128'h%32h", key_in[255:128]);`
167			`// announce key expansion is not done again`
168			`$display("Using the same key, expansion is not required.");`
169			`$display("");`
170
171			`// first cipher text input data`
172			`data_in[127:0] <= 128'hef0bc156ed8ff21223f247b3e0318a99;`
173			`data_in_valid <= 1'b1;`
174			`@ (posedge clock);`
175			`// display data value`
176			`$display("Ciphertext Data 1: 128'h%32h", data_in);`
177			`// second cipher text input data`
178			`data_in[127:0] <= 128'hf91914cd01924b124c2ec316b4b35a79;`
179			`data_in_valid <= 1'b1;`
180			`@ (posedge clock);`
181			`// display data value`
182			`$display("Ciphertext Data 2: 128'h%32h", data_in);`
183			`// third cipher text input data`
184			`data_in[127:0] <= 128'h8df4e9aac5c7573a27d8d055d6e4d64b;`
185			`data_in_valid <= 1'b1;`
186			`@ (posedge clock);`
187			`// display data value`
188			`$display("Ciphertext Data 3: 128'h%32h", data_in);`
189			`// forth cipher text input data`
190			`data_in[127:0] <= 128'hec8ce641087165a463d4118dc35f9001;`
191			`data_in_valid <= 1'b1;`
192			`@ (posedge clock);`
193			`// display data value`
194			`$display("Ciphertext Data 4: 128'h%32h", data_in);`
195			`// no more data can be given to the core`
196			`data_in_valid <= 1'b0;`
197
198			`// announce state`
199			`$display("");`
200			`$display("Waiting for plain text data");`
201
202			`// wait for all output plain text data`
203			`dout_count = 0;`
204			`while (dout_count < 4)`
205			`begin`
206			`// check for a new output data`
207			`if (data_out_valid)`
208			`dout_count <= dout_count + 1;`
209			`// wait for next clock cycle`
210			`@(posedge clock);`
211			`end`
212			`$display("");`
213
214			`// encryption for 192 bit key mode`
215			`$display("Testing encryption for 192 bit key:");`
216			`$display("-------------------------------------");`
217			`// set core mode to encryption and key size to 192`
218			`enc_dec <= 1'b0;`
219			`key_mode <= 2'b01;`
220			`// set the key value and start key expansion`
221			`key_in[255:64] <= 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;`
222			`key_start <= 1'b1;`
223			`@(posedge clock);`
224			`key_start <= 1'b0;`
225			`@(posedge clock);`
226			`// display key value`
227			`$display("Key: 192'h%32h", key_in[255:64]);`
228			`// wait for key expansion to finish`
229			`while (!key_ready) @(posedge clock);`
230			`// announce key expansion ended`
231			`$display("Key expansion done");`
232			`$display("");`
233
234			`// first plain text input data`
235			`data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;`
236			`data_in_valid <= 1'b1;`
237			`@ (posedge clock);`
238			`// display data value`
239			`$display("Plaintext Data 1: 128'h%32h", data_in);`
240			`// second plain text input data`
241			`data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;`
242			`data_in_valid <= 1'b1;`
243			`@ (posedge clock);`
244			`// display data value`
245			`$display("Plaintext Data 2: 128'h%32h", data_in);`
246			`// third plain text input data`
247			`data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;`
248			`data_in_valid <= 1'b1;`
249			`@ (posedge clock);`
250			`// display data value`
251			`$display("Plaintext Data 3: 128'h%32h", data_in);`
252			`// forth plain text input data`
253			`data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;`
254			`data_in_valid <= 1'b1;`
255			`@ (posedge clock);`
256			`// display data value`
257			`$display("Plaintext Data 4: 128'h%32h", data_in);`
258			`// no more data can be given to the core`
259			`data_in_valid <= 1'b0;`
260			`@(posedge clock);`
261
262			`// announce state`
263			`$display("");`
264			`$display("Waiting for cipher text data");`
265
266			`// wait for all output cipher text data`
267			`dout_count = 0;`
268			`while (dout_count < 4)`
269			`begin`
270			`// check for a new output data`
271			`if (data_out_valid)`
272			`dout_count <= dout_count + 1;`
273			`// wait for next clock cycle`
274			`@(posedge clock);`
275			`end`
276			`$display("");`
277
278			`// continue with decryption of the same cipher text without key expansion`
279			`$display("Testing decryption for 192 bit key:");`
280			`$display("-------------------------------------");`
281			`// set core mode to decryption`
282			`enc_dec <= 1'b1;`
283			`@(posedge clock);`
284			`// display key value`
285			`$display("Key: 192'h%32h", key_in[255:64]);`
286			`// announce key expansion is not done again`
287			`$display("Using the same key, expansion is not required.");`
288			`$display("");`
289
290			`// first cipher text input data`
291			`data_in[127:0] <= 128'h17d3cbb6a98f64ccd134e0d0b7695aa9;`
292			`data_in_valid <= 1'b1;`
293			`@ (posedge clock);`
294			`// display data value`
295			`$display("Ciphertext Data 1: 128'h%32h", data_in);`
296			`// second cipher text input data`
297			`data_in[127:0] <= 128'h4a7d86377de2a8faf00f8ef97c2eb982;`
298			`data_in_valid <= 1'b1;`
299			`@ (posedge clock);`
300			`// display data value`
301			`$display("Ciphertext Data 2: 128'h%32h", data_in);`
302			`// third cipher text input data`
303			`data_in[127:0] <= 128'heb1b03f2acb64bcf28c9991cc8a4fa50;`
304			`data_in_valid <= 1'b1;`
305			`@ (posedge clock);`
306			`// display data value`
307			`$display("Ciphertext Data 3: 128'h%32h", data_in);`
308			`// forth cipher text input data`
309			`data_in[127:0] <= 128'h2adc503e1c9b669de6b5bc904035547d;`
310			`data_in_valid <= 1'b1;`
311			`@ (posedge clock);`
312			`// display data value`
313			`$display("Ciphertext Data 4: 128'h%32h", data_in);`
314			`// no more data can be given to the core`
315			`data_in_valid <= 1'b0;`
316
317			`// announce state`
318			`$display("");`
319			`$display("Waiting for plain text data");`
320
321			`// wait for all output plain text data`
322			`dout_count = 0;`
323			`while (dout_count < 4)`
324			`begin`
325			`// check for a new output data`
326			`if (data_out_valid)`
327			`dout_count <= dout_count + 1;`
328			`// wait for next clock cycle`
329			`@(posedge clock);`
330			`end`
331			`$display("");`
332
333			`// encryption for 256 bit key mode`
334			`$display("Testing encryption for 256 bit key:");`
335			`$display("-------------------------------------");`
336			`// set core mode to encryption and key size to 256`
337			`enc_dec <= 1'b0;`
338			`key_mode <= 2'b10;`
339			`// set the key value and start key expansion`
340			`key_in[255:0] <= 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;`
341			`key_start <= 1'b1;`
342			`@(posedge clock);`
343			`key_start <= 1'b0;`
344			`@(posedge clock);`
345			`// display key value`
346			`$display("Key: 256'h%32h", key_in[255:64]);`
347			`// wait for key expansion to finish`
348			`while (!key_ready) @(posedge clock);`
349			`// announce key expansion ended`
350			`$display("Key expansion done");`
351			`$display("");`
352
353			`// first plain text input data`
354			`data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;`
355			`data_in_valid <= 1'b1;`
356			`@ (posedge clock);`
357			`// display data value`
358			`$display("Plaintext Data 1: 128'h%32h", data_in);`
359			`// second plain text input data`
360			`data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;`
361			`data_in_valid <= 1'b1;`
362			`@ (posedge clock);`
363			`// display data value`
364			`$display("Plaintext Data 2: 128'h%32h", data_in);`
365			`// third plain text input data`
366			`data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;`
367			`data_in_valid <= 1'b1;`
368			`@ (posedge clock);`
369			`// display data value`
370			`$display("Plaintext Data 3: 128'h%32h", data_in);`
371			`// forth plain text input data`
372			`data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;`
373			`data_in_valid <= 1'b1;`
374			`@ (posedge clock);`
375			`// display data value`
376			`$display("Plaintext Data 4: 128'h%32h", data_in);`
377			`// no more data can be given to the core`
378			`data_in_valid <= 1'b0;`
379			`@(posedge clock);`
380
381			`// announce state`
382			`$display("");`
383			`$display("Waiting for cipher text data");`
384
385			`// wait for all output cipher text data`
386			`dout_count = 0;`
387			`while (dout_count < 4)`
388			`begin`
389			`// check for a new output data`
390			`if (data_out_valid)`
391			`dout_count <= dout_count + 1;`
392			`// wait for next clock cycle`
393			`@(posedge clock);`
394			`end`
395			`$display("");`
396
397			`// continue with decryption of the same cipher text without key expansion`
398			`$display("Testing decryption for 256 bit key:");`
399			`$display("-------------------------------------");`
400			`// set core mode to decryption`
401			`enc_dec <= 1'b1;`
402			`@(posedge clock);`
403			`// display key value`
404			`$display("Key: 256'h%32h", key_in[255:0]);`
405			`// announce key expansion is not done again`
406			`$display("Using the same key, expansion is not required.");`
407			`$display("");`
408
409			`// first cipher text input data`
410			`data_in[127:0] <= 128'h32573d9003bfd345029779298be53b96;`
411			`data_in_valid <= 1'b1;`
412			`@ (posedge clock);`
413			`// display data value`
414			`$display("Ciphertext Data 1: 128'h%32h", data_in);`
415			`// second cipher text input data`
416			`data_in[127:0] <= 128'ha5f464b57512d05db2bae8d2415b921d;`
417			`data_in_valid <= 1'b1;`
418			`@ (posedge clock);`
419			`// display data value`
420			`$display("Ciphertext Data 2: 128'h%32h", data_in);`
421			`// third cipher text input data`
422			`data_in[127:0] <= 128'hd83414223d20a0c928b136c884d07ea2;`
423			`data_in_valid <= 1'b1;`
424			`@ (posedge clock);`
425			`// display data value`
426			`$display("Ciphertext Data 3: 128'h%32h", data_in);`
427			`// forth cipher text input data`
428			`data_in[127:0] <= 128'hc1f968d2a6859137bd9ad9111ad7f6dc;`
429			`data_in_valid <= 1'b1;`
430			`@ (posedge clock);`
431			`// display data value`
432			`$display("Ciphertext Data 4: 128'h%32h", data_in);`
433			`// no more data can be given to the core`
434			`data_in_valid <= 1'b0;`
435
436			`// announce state`
437			`$display("");`
438			`$display("Waiting for plain text data");`
439
440			`// wait for all output plain text data`
441			`dout_count = 0;`
442			`while (dout_count < 4)`
443			`begin`
444			`// check for a new output data`
445			`if (data_out_valid)`
446			`dout_count <= dout_count + 1;`
447			`// wait for next clock cycle`
448			`@(posedge clock);`
449			`end`
450			`$display("");`
451
452			`// announce simulation end`
453			`$display(" Simulation Done !!!");`
454
455			`repeat (10) @(posedge clock);`
456	6	motilito	`$finish;`
457			`end`
458
459	8	motilito	`// unit under test`
460			`aes dut`
461			`(`
462			`.clk(clock),`
463			`.reset(reset),`
464			`.i_start(key_start),`
465			`.i_enable(enable),`
466			`.i_ende(enc_dec),`
467			`.i_key(key_in),`
468			`.i_key_mode(key_mode),`
469			`.i_data(data_in),`
470			`.i_data_valid(data_in_valid),`
471			`.o_ready(ready_out),`
472			`.o_data(data_out),`
473			`.o_data_valid(data_out_valid),`
474			`.o_key_ready(key_ready)`
475	6	motilito	`);`
476
477	8	motilito	`// display output data from the core`
478			`always @ (posedge clock)`
479	6	motilito	`if (data_out_valid)`
480	8	motilito	`$display("Output Data %1d: 128'h%16h", dout_count+1, data_out);`
481	6	motilito
482			`endmodule`
483	8	motilito	`//---------------------------------------------------------------------------------------`
484			`// Th.. Th.. Th.. Thats all folks !!!`
485			`//---------------------------------------------------------------------------------------`

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