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[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [key_exp.v] - Blame information for rev 7

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1 5 motilito 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Key expansion module                                        ////
4 
////                                                              ////
5 
////  Description:                                                ////
6 
////  Used to expand the key based on key expansion procudure     ////
7 
////                                                              ////
8 
////  To Do:                                                      ////
9 
////   - done                                                     ////
10 
////                                                              ////
11 
////  Author(s):                                                  ////
12 
////      - Luo Dongjun,   dongjun_luo@hotmail.com                ////
13 
////                                                              ////
14 
//////////////////////////////////////////////////////////////////////
15 
module key_exp (
16 
   clk,
17 7 motilito 
   reset,
18 5 motilito 
   key_in,
19 
   key_mode,
20 
   key_start,
21 
   wr,
22 
   wr_addr,
23 
   wr_data,
24 
   key_ready
25 
);
26 
 
27 
input             clk;
28 7 motilito 
input             reset;
29 5 motilito 
input   [255:0]   key_in;   // initial key value
30 
input   [1:0]     key_mode; // 0:128, 1:192, 2:256
31 
input             key_start;// start key expansion
32 
output            wr;       // key expansion ram interface
33 
output  [4:0]     wr_addr;
34 
output  [63:0]    wr_data;
35 
output            key_ready;
36 
 
37 
reg [31:0]  rcon;
38 
reg         rcon_is_1b;
39 
reg [1:0]   state,nstate,pstate;
40 
reg [3:0]   round;
41 
reg         sbox_in_valid;
42 
reg [31:0]  sbox_in;
43 
reg [4:0]   valid;
44 
wire        sbox_out_valid;
45 
wire [31:0] sbox_out;
46 
wire [31:0] w0_next,w1_next,w2_next,w3_next,w4_next1,w5_next1,w6_next,w7_next;
47 
wire [31:0] w4_next2,w5_next2;
48 
reg [31:0]  w0,w1,w2,w3,w4,w5,w6,w7;
49 
wire        wr1,wr2,wr3,init_wr1,init_wr2,init_wr3,init_wr4;
50 
reg         wr;
51 
wire [63:0] wr_data1,wr_data2,wr_data3;
52 
reg         key_start_L,key_start_L2,key_start_L3;
53 
reg         wr_256;
54 
reg [4:0]   wr_addr;
55 
reg [63:0]  wr_data;
56 
reg         key_ready;
57 
wire   [3:0] max_round_p1;
58 
 
59 
parameter   IDLE       = 2'b00,
60 
            START      = 2'b01,
61 
            GENKEY1    = 2'b10,
62 
            GENKEY_256 = 2'b11;
63 
 
64 
assign max_round_p1[3:0] = (key_mode == 2'b00) ? 4'd11 : (key_mode == 2'b01 ? 4'd13 : 4'd15);
65 
 
66 
// rcon generation
67 7 motilito 
always @ (posedge clk or posedge reset)
68 5 motilito 
begin
69 7 motilito 
   if (reset)
70 5 motilito 
   begin
71 
      rcon[31:0] <= 32'h01000000;
72 
      rcon_is_1b <= 1'b0;
73 
   end
74 
   else if (key_start)
75 
   begin
76 
      rcon[31:0] <= 32'h01000000;
77 
      rcon_is_1b <= 1'b0;
78 
   end
79 
   else if (sbox_out_valid && (state[1:0] == GENKEY1))
80 
   begin
81 
      if (rcon[31])
82 
      begin
83 
         rcon[31:0] <= 32'h1b000000;
84 
         rcon_is_1b <= 1'b1;
85 
      end
86 
      else if (rcon_is_1b)
87 
      begin
88 
         rcon[31:0] <= 32'h36000000;
89 
         rcon_is_1b <= 1'b1;
90 
      end
91 
      else
92 
         rcon[31:0] <= {rcon[30:0],1'b0};
93 
   end
94 
end
95 
 
96 
/*****************************************************************************/
97 
// State machine for Key expansion
98 
//
99 
//
100 7 motilito 
always @ (posedge clk or posedge reset)
101 5 motilito 
begin
102 7 motilito 
   if (reset)
103 5 motilito 
   begin
104 
      state[1:0]  <= IDLE;
105 
      pstate[1:0] <= IDLE;
106 
   end
107 
   else
108 
   begin
109 
      state[1:0]  <= nstate[1:0];
110 
      pstate[1:0] <= state[1:0];
111 
   end
112 
end
113 
 
114 
always @ (*)
115 
begin
116 
   nstate[1:0] = state[1:0];
117 
   case (state[1:0])
118 
      IDLE:
119 
         if (key_start) nstate[1:0] = START;
120 
      START:
121 
      begin
122 
         nstate[1:0] = GENKEY1;
123 
      end
124 
      GENKEY1:
125 
      begin
126 
         if (sbox_out_valid)
127 
         begin
128 
            if (key_mode == 2'b00) //128 bit mode 4 x 10 + 4
129 
               if (round[3:0] == 4'd10)   nstate[1:0] = IDLE;
130 
               else                       nstate[1:0] = START;
131 
            else if (key_mode == 2'b01) // 192 bit mode 6 + 6 x 8 = 54 > 52
132 
               if (round[3:0] == 4'd8) nstate[1:0] = IDLE;
133 
               else                    nstate[1:0] = START;
134 
            else if (round[3:0] == 4'd7)// 256 bit mode 8 + 8 x 7 = 64 > 60
135 
               nstate[1:0] = IDLE;
136 
            else
137 
               nstate[1:0] = GENKEY_256;
138 
         end
139 
      end
140 
      GENKEY_256:
141 
      begin
142 
         if (sbox_out_valid)
143 
            nstate[1:0] = START;
144 
      end
145 
   endcase
146 
end
147 
 
148 
// round counter: 10/12/14
149 7 motilito 
always @ (posedge clk or posedge reset)
150 5 motilito 
begin
151 7 motilito 
   if (reset)
152 5 motilito 
      round[3:0] <= 1'b0;
153 
   else if (nstate[1:0] == IDLE)
154 
      round[3:0] <= 4'b0;
155 
   else if (state[1:0] == START)
156 
      round[3:0] <= round[3:0] + 1'b1;
157 
end
158 
 
159 7 motilito 
always @ (posedge clk or posedge reset)
160 5 motilito 
begin
161 7 motilito 
   if (reset)
162 5 motilito 
   begin
163 
      sbox_in_valid <= 1'b0;
164 
      sbox_in[31:0] <= 32'b0;
165 
   end
166 
   else if (state[1:0] == START) // rotword
167 
   begin
168 
      sbox_in_valid <= 1'b1;
169 
      if (key_mode == 2'b00) //128
170 
         sbox_in[31:0] <= {w3[23:0],w3[31:24]};
171 
      else if (key_mode == 2'b01) //192
172 
         sbox_in[31:0] <= {w5[23:0],w5[31:24]};
173 
      else //256
174 
         sbox_in[31:0] <= {w7[23:0],w7[31:24]};
175 
   end
176 
   else if ((state[1:0] == GENKEY_256) && (pstate[1:0] ==GENKEY1))
177 
   begin
178 
      sbox_in_valid <= 1'b1;
179 
      sbox_in[31:0] <= w3[31:0];
180 
   end
181 
   else
182 
      sbox_in_valid <= 1'b0;
183 
end
184 
 
185 7 motilito 
always @ (posedge clk or posedge reset)
186 5 motilito 
begin
187 7 motilito 
   if (reset)
188 5 motilito 
      valid[4:0] <= 5'b0;
189 
   else
190 
      valid[4:0] <= {valid[3:0],sbox_in_valid};
191 
end
192 
assign sbox_out_valid = valid[1];
193 
 
194 7 motilito 
sbox u_0(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[7:0]),.ende(1'b0),.en_dout(sbox_out[7:0]),.de_dout());
195 
sbox u_1(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[15:8]),.ende(1'b0),.en_dout(sbox_out[15:8]),.de_dout());
196 
sbox u_2(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[23:16]),.ende(1'b0),.en_dout(sbox_out[23:16]),.de_dout());
197 
sbox u_3(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[31:24]),.ende(1'b0),.en_dout(sbox_out[31:24]),.de_dout());
198 5 motilito 
 
199 
/*****************************************************************************/
200 
// key expansion calculation
201 
//
202 
//
203 
assign w0_next[31:0] = sbox_out[31:0]^rcon[31:0]^w0[31:0];
204 
assign w1_next[31:0] = w0_next[31:0]^w1[31:0];
205 
assign w2_next[31:0] = w1_next[31:0]^w2[31:0];
206 
assign w3_next[31:0] = w2_next[31:0]^w3[31:0];
207 
assign w4_next1[31:0] = w3_next[31:0] ^ w4[31:0];
208 
assign w5_next1[31:0] = w4_next1[31:0]^w5[31:0];
209 
assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0];
210 
assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0];
211 
assign w6_next[31:0] = w5_next2[31:0]^w6[31:0];
212 
assign w7_next[31:0] = w6_next[31:0]^w7[31:0];
213 
 
214 7 motilito 
always @ (posedge clk or posedge reset)
215 5 motilito 
begin
216 7 motilito 
   if (reset)
217 5 motilito 
   begin
218 
      {w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= 256'b0;
219 
   end
220 
   else if (key_start)
221 
   begin
222 
      {w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= key_in[255:0];
223 
   end
224 
   else if ((key_mode[1:0] == 2'b10) && sbox_out_valid)
225 
   begin
226 
      if (state[1:0] == GENKEY1)
227 
      begin
228 
         w0[31:0] <= w0_next[31:0];
229 
         w1[31:0] <= w1_next[31:0];
230 
         w2[31:0] <= w2_next[31:0];
231 
         w3[31:0] <= w3_next[31:0];
232 
      end
233 
      else
234 
      begin
235 
         w4[31:0] <= w4_next2[31:0];
236 
         w5[31:0] <= w5_next2[31:0];
237 
         w6[31:0] <= w6_next[31:0];
238 
         w7[31:0] <= w7_next[31:0];
239 
      end
240 
   end
241 
   else if (sbox_out_valid)
242 
   begin
243 
      w0[31:0] <= w0_next[31:0];
244 
      w1[31:0] <= w1_next[31:0];
245 
      w2[31:0] <= w2_next[31:0];
246 
      w3[31:0] <= w3_next[31:0];
247 
      if (key_mode[1:0] == 2'b01)
248 
      begin
249 
         w4[31:0] <= w4_next1[31:0];
250 
         w5[31:0] <= w5_next1[31:0];
251 
      end
252 
   end
253 
end
254 
 
255 
// write to external ram
256 
assign init_wr1 = key_start;
257 
assign init_wr2 = key_start_L;
258 
assign init_wr3 = key_start_L2 && (key_mode[1:0] != 2'b00);
259 
assign init_wr4 = key_start_L3 && (key_mode[1:0] == 2'b10);
260 
assign wr1 = valid[2];
261 
assign wr2 = valid[3];
262 
assign wr3 = valid[4] && (key_mode[1:0] == 2'b01) && (state[1:0] != IDLE); // remove the last write
263 
 
264 
assign wr_data1[63:0] = wr_256 ?{w4[31:0],w5[31:0]} : {w0[31:0],w1[31:0]};
265 
assign wr_data2[63:0] = wr_256 ?{w6[31:0],w7[31:0]} : {w2[31:0],w3[31:0]};
266 
assign wr_data3[63:0] = {w4[31:0],w5[31:0]};
267 
 
268 7 motilito 
always @ (posedge clk or posedge reset)
269 5 motilito 
begin
270 7 motilito 
   if (reset)
271 5 motilito 
      wr_256 <= 1'b0;
272 
   else if (key_start)
273 
      wr_256 <= 1'b0;
274 
   else if (sbox_out_valid && (state[1:0] == GENKEY_256))
275 
      wr_256 <= 1'b1;
276 
   else if (sbox_out_valid)
277 
      wr_256 <= 1'b0;
278 
end
279 
 
280 7 motilito 
always @ (posedge clk or posedge reset)
281 5 motilito 
begin
282 7 motilito 
   if (reset)
283 5 motilito 
      {key_start_L3,key_start_L2,key_start_L} <= 3'b0;
284 
   else
285 
      {key_start_L3,key_start_L2,key_start_L} <= {key_start_L2,key_start_L,key_start};
286 
end
287 
 
288 7 motilito 
always @ (posedge clk or posedge reset)
289 5 motilito 
begin
290 7 motilito 
   if (reset)
291 5 motilito 
      wr <= 1'b0;
292 
   else
293 
      wr <= wr1 || wr2 || wr3 || init_wr1 || init_wr2 || init_wr3 || init_wr4;
294 
end
295 
 
296 7 motilito 
always @ (posedge clk or posedge reset)
297 5 motilito 
begin
298 7 motilito 
   if (reset)
299 5 motilito 
   begin
300 
      wr_data[63:0] <= 64'b0;
301 
   end
302 
   else
303 
   begin
304 
      if (init_wr1)
305 
         wr_data[63:0] <= key_in[255:192];
306 
      else if (init_wr2)
307 
         wr_data[63:0] <= key_in[191:128];
308 
      else if (init_wr3)
309 
         wr_data[63:0] <= key_in[127:64];
310 
      else if (init_wr4)
311 
         wr_data[63:0] <= key_in[63:0];
312 
      else if (wr1)
313 
         wr_data[63:0] <= wr_data1[63:0];
314 
      else if (wr2)
315 
         wr_data[63:0] <= wr_data2[63:0];
316 
      else if (wr3)
317 
         wr_data[63:0] <= wr_data3[63:0];
318 
   end
319 
end
320 
 
321 7 motilito 
always @ (posedge clk or posedge reset)
322 5 motilito 
begin
323 7 motilito 
   if (reset)
324 5 motilito 
      wr_addr[4:0] <= 5'b0;
325 
   else if (key_start)
326 
      wr_addr[4:0] <= 5'd0;
327 
   else if (wr)
328 
      wr_addr[4:0] <= wr_addr[4:0] + 1'b1;
329 
end
330 
 
331 7 motilito 
always @ (posedge clk or posedge reset)
332 5 motilito 
begin
333 7 motilito 
   if (reset)
334 5 motilito 
      key_ready <= 1'b0;
335 
   else if (key_start)
336 
      key_ready <= 1'b0;
337 
   else if (wr_addr[4:1] == max_round_p1[3:0])
338 
      key_ready <= 1'b1;
339 
end
340 
endmodule

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