OpenCores
URL https://opencores.org/ocsvn/all-pole_filters/all-pole_filters/trunk

Subversion Repositories all-pole_filters

[/] [all-pole_filters/] [trunk/] [Testbenches/] [filter_tb.vhd] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 fcorthay 
--##############################################################################
2 
--
3 
--  filter_tb
4 
--      Testbench for digital lowpass filters
5 
--
6 
--      This testbench has one architecture per filter to test.
7 
--      The tester itself is given in a separate file: "filter_tester.vhd".
8 
--
9 
--------------------------------------------------------------------------------
10 
--
11 
--  Versions / Authors
12 
--      1.0 Francois Corthay    first implementation
13 
--
14 
--  Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
15 
--
16 
--  by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
17 
--  <http://isi.hevs.ch/switzerland/robust-electronics.html>.
18 
--
19 
--------------------------------------------------------------------------------
20 
--
21 
--  Usage
22 
--      The usage can vary from on EDA tool to another. However, it can be
23 
--      used with a minimal preparation in the standard library "work".
24 
--
25 
--      Compile the filter to test and the filter tester (see
26 
--      "filter_tester.vhd").
27 
--
28 
--      Choose the test architecture: comment-out the others or rely on the
29 
--      possibilities of your EDA tool.
30 
--
31 
--      Compile and go.
32 
--
33 
--##############################################################################
34 
 
35 
LIBRARY ieee;
36 
  USE ieee.std_logic_1164.all;
37 
  USE ieee.numeric_std.ALL;
38 
 
39 
ENTITY filter_tb IS
40 
END filter_tb ;
41 
 
42 
--==============================================================================
43 
 
44 
ARCHITECTURE butterworth3 OF filter_tb IS
45 
 
46 
  constant inputBitNb: positive := 16;
47 
  constant outputBitNb: positive := 20;
48 
  constant shiftBitNb: positive := 8;
49 
 
50 
  SIGNAL clock     : std_ulogic;
51 
  SIGNAL en        : std_ulogic;
52 
  SIGNAL filterIn  : signed(inputBitNb-1 DOWNTO 0);
53 
  SIGNAL filterOut : signed(outputBitNb-1 DOWNTO 0);
54 
  SIGNAL reset     : std_ulogic;
55 
 
56 
  COMPONENT butterworth3
57 
  GENERIC (
58 
    inputBitNb  : positive := 16;
59 
    outputBitNb : positive := 16;
60 
    shiftBitNb  : positive := 4
61 
  );
62 
  PORT (
63 
    filterOut : OUT    signed (outputBitNb-1 DOWNTO 0);
64 
    filterIn  : IN     signed (inputBitNb-1 DOWNTO 0);
65 
    clock     : IN     std_ulogic ;
66 
    reset     : IN     std_ulogic ;
67 
    en        : IN     std_ulogic
68 
  );
69 
  END COMPONENT;
70 
 
71 
  COMPONENT filter_tester
72 
  GENERIC (
73 
    inputBitNb  : positive := 16;
74 
    outputBitNb : positive := 16;
75 
    shiftBitNb  : positive := 16
76 
  );
77 
  PORT (
78 
    reset     : OUT    std_ulogic ;
79 
    clock     : OUT    std_ulogic ;
80 
    filterOut : IN     signed (outputBitNb-1 DOWNTO 0);
81 
    en        : OUT    std_ulogic ;
82 
    filterIn  : OUT    signed (inputBitNb-1 DOWNTO 0)
83 
  );
84 
  END COMPONENT;
85 
 
86 
BEGIN
87 
 
88 
  DUT : butterworth3
89 
    GENERIC MAP (
90 
      inputBitNb  => inputBitNb,
91 
      outputBitNb => outputBitNb,
92 
      shiftBitNb  => shiftBitNb
93 
    )
94 
    PORT MAP (
95 
      filterOut => filterOut,
96 
      filterIn  => filterIn,
97 
      clock     => clock,
98 
      reset     => reset,
99 
      en        => en
100 
    );
101 
 
102 
  Tester : filter_tester
103 
    GENERIC MAP (
104 
      inputBitNb  => inputBitNb,
105 
      outputBitNb => outputBitNb,
106 
      shiftBitNb  => shiftBitNb
107 
    )
108 
    PORT MAP (
109 
      reset     => reset,
110 
      clock     => clock,
111 
      filterOut => filterOut,
112 
      en        => en,
113 
      filterIn  => filterIn
114 
     );
115 
 
116 
END butterworth3;
117 
 
118 
--==============================================================================
119 
 
120 
ARCHITECTURE bessel6 OF filter_tb IS
121 
 
122 
  constant inputBitNb: positive := 16;
123 
  constant outputBitNb: positive := 20;
124 
  constant shiftBitNb: positive := 8;
125 
 
126 
  SIGNAL clock     : std_ulogic;
127 
  SIGNAL en        : std_ulogic;
128 
  SIGNAL filterIn  : signed(inputBitNb-1 DOWNTO 0);
129 
  SIGNAL filterOut : signed(outputBitNb-1 DOWNTO 0);
130 
  SIGNAL reset     : std_ulogic;
131 
 
132 
  COMPONENT bessel6
133 
  GENERIC (
134 
    inputBitNb  : positive := 16;
135 
    outputBitNb : positive := 16;
136 
    shiftBitNb  : positive := 4
137 
  );
138 
  PORT (
139 
    filterOut : OUT    signed (outputBitNb-1 DOWNTO 0);
140 
    filterIn  : IN     signed (inputBitNb-1 DOWNTO 0);
141 
    clock     : IN     std_ulogic ;
142 
    reset     : IN     std_ulogic ;
143 
    en        : IN     std_ulogic
144 
  );
145 
  END COMPONENT;
146 
 
147 
  COMPONENT filter_tester
148 
  GENERIC (
149 
    inputBitNb  : positive := 16;
150 
    outputBitNb : positive := 16;
151 
    shiftBitNb  : positive := 16
152 
  );
153 
  PORT (
154 
    reset     : OUT    std_ulogic ;
155 
    clock     : OUT    std_ulogic ;
156 
    filterOut : IN     signed (outputBitNb-1 DOWNTO 0);
157 
    en        : OUT    std_ulogic ;
158 
    filterIn  : OUT    signed (inputBitNb-1 DOWNTO 0)
159 
  );
160 
  END COMPONENT;
161 
 
162 
BEGIN
163 
 
164 
  DUT : bessel6
165 
    GENERIC MAP (
166 
      inputBitNb  => inputBitNb,
167 
      outputBitNb => outputBitNb,
168 
      shiftBitNb  => shiftBitNb
169 
    )
170 
    PORT MAP (
171 
      filterOut => filterOut,
172 
      filterIn  => filterIn,
173 
      clock     => clock,
174 
      reset     => reset,
175 
      en        => en
176 
    );
177 
 
178 
  Tester : filter_tester
179 
    GENERIC MAP (
180 
      inputBitNb  => inputBitNb,
181 
      outputBitNb => outputBitNb,
182 
      shiftBitNb  => shiftBitNb
183 
    )
184 
    PORT MAP (
185 
      reset     => reset,
186 
      clock     => clock,
187 
      filterOut => filterOut,
188 
      en        => en,
189 
      filterIn  => filterIn
190 
     );
191 
 
192 
END bessel6;
193 
 
194 
--==============================================================================
195 
 
196 
ARCHITECTURE bessel8 OF filter_tb IS
197 
 
198 
   constant inputBitNb: positive := 16;
199 
   constant outputBitNb: positive := 20;
200 
   constant shiftBitNb: positive := 8;
201 
 
202 
   SIGNAL clock     : std_ulogic;
203 
   SIGNAL en        : std_ulogic;
204 
   SIGNAL filterIn  : signed(inputBitNb-1 DOWNTO 0);
205 
   SIGNAL filterOut : signed(outputBitNb-1 DOWNTO 0);
206 
   SIGNAL reset     : std_ulogic;
207 
 
208 
  COMPONENT bessel8
209 
  GENERIC (
210 
    inputBitNb  : positive := 16;
211 
    outputBitNb : positive := 16;
212 
    shiftBitNb  : positive := 4
213 
  );
214 
  PORT (
215 
    filterOut : OUT    signed (outputBitNb-1 DOWNTO 0);
216 
    filterIn  : IN     signed (inputBitNb-1 DOWNTO 0);
217 
    clock     : IN     std_ulogic ;
218 
    reset     : IN     std_ulogic ;
219 
    en        : IN     std_ulogic
220 
  );
221 
  END COMPONENT;
222 
 
223 
  COMPONENT filter_tester
224 
  GENERIC (
225 
    inputBitNb  : positive := 16;
226 
    outputBitNb : positive := 16;
227 
    shiftBitNb  : positive := 16
228 
  );
229 
  PORT (
230 
    reset     : OUT    std_ulogic ;
231 
    clock     : OUT    std_ulogic ;
232 
    filterOut : IN     signed (outputBitNb-1 DOWNTO 0);
233 
    en        : OUT    std_ulogic ;
234 
    filterIn  : OUT    signed (inputBitNb-1 DOWNTO 0)
235 
  );
236 
  END COMPONENT;
237 
 
238 
BEGIN
239 
 
240 
  DUT : bessel8
241 
    GENERIC MAP (
242 
      inputBitNb  => inputBitNb,
243 
      outputBitNb => outputBitNb,
244 
      shiftBitNb  => shiftBitNb
245 
    )
246 
    PORT MAP (
247 
      filterOut => filterOut,
248 
      filterIn  => filterIn,
249 
      clock     => clock,
250 
      reset     => reset,
251 
      en        => en
252 
    );
253 
 
254 
  Tester : filter_tester
255 
    GENERIC MAP (
256 
      inputBitNb  => inputBitNb,
257 
      outputBitNb => outputBitNb,
258 
      shiftBitNb  => shiftBitNb
259 
    )
260 
    PORT MAP (
261 
      reset     => reset,
262 
      clock     => clock,
263 
      filterOut => filterOut,
264 
      en        => en,
265 
      filterIn  => filterIn
266 
     );
267 
 
268 
END bessel8;
269 
 
270 
--==============================================================================
271 
 
272 
ARCHITECTURE lowpass OF filter_tb IS
273 
 
274 
   constant inputBitNb: positive := 16;
275 
   constant outputBitNb: positive := 20;
276 
   constant shiftBitNb: positive := 8;
277 
 
278 
   SIGNAL clock     : std_ulogic;
279 
   SIGNAL en        : std_ulogic;
280 
   SIGNAL filterIn  : signed(inputBitNb-1 DOWNTO 0);
281 
   SIGNAL filterOut : signed(outputBitNb-1 DOWNTO 0);
282 
   SIGNAL reset     : std_ulogic;
283 
 
284 
  COMPONENT lowpass
285 
  GENERIC (
286 
    inputBitNb  : positive := 16;
287 
    outputBitNb : positive := 16;
288 
    shiftBitNb  : positive := 4
289 
  );
290 
  PORT (
291 
    filterOut : OUT    signed (outputBitNb-1 DOWNTO 0);
292 
    filterIn  : IN     signed (inputBitNb-1 DOWNTO 0);
293 
    clock     : IN     std_ulogic ;
294 
    reset     : IN     std_ulogic ;
295 
    en        : IN     std_ulogic
296 
  );
297 
  END COMPONENT;
298 
 
299 
  COMPONENT filter_tester
300 
  GENERIC (
301 
    inputBitNb  : positive := 16;
302 
    outputBitNb : positive := 16;
303 
    shiftBitNb  : positive := 16
304 
  );
305 
  PORT (
306 
    reset     : OUT    std_ulogic ;
307 
    clock     : OUT    std_ulogic ;
308 
    filterOut : IN     signed (outputBitNb-1 DOWNTO 0);
309 
    en        : OUT    std_ulogic ;
310 
    filterIn  : OUT    signed (inputBitNb-1 DOWNTO 0)
311 
  );
312 
  END COMPONENT;
313 
 
314 
BEGIN
315 
 
316 
  DUT : lowpass
317 
    GENERIC MAP (
318 
      inputBitNb  => inputBitNb,
319 
      outputBitNb => outputBitNb,
320 
      shiftBitNb  => shiftBitNb
321 
    )
322 
    PORT MAP (
323 
      filterOut => filterOut,
324 
      filterIn  => filterIn,
325 
      clock     => clock,
326 
      reset     => reset,
327 
      en        => en
328 
    );
329 
 
330 
  Tester : filter_tester
331 
    GENERIC MAP (
332 
      inputBitNb  => inputBitNb,
333 
      outputBitNb => outputBitNb,
334 
      shiftBitNb  => shiftBitNb
335 
    )
336 
    PORT MAP (
337 
      reset     => reset,
338 
      clock     => clock,
339 
      filterOut => filterOut,
340 
      en        => en,
341 
      filterIn  => filterIn
342 
     );
343 
 
344 
END bessel8;
345 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.