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[/] [amber/] [trunk/] [hw/] [fpga/] [bin/] [xs6_source_files.prj] - Blame information for rev 77

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# ----------------------------------------------------------------
#                                                               //
#   Xilinx Spartan-6 FPGA synthesis Verilog source file list    //
#                                                               //
#   This file is part of the Amber project                      //
#   http://www.opencores.org/project,amber                      //
#                                                               //
#   Description                                                 //
#                                                               //
#   Author(s):                                                  //
#       - Conor Santifort, csantifort.amber@gmail.com           //
#                                                               //
#/ ///////////////////////////////////////////////////////////////
#                                                               //
#  Copyright (C) 2010 Authors and OPENCORES.ORG                 //
#                                                               //
#  This source file may be used and distributed without         //
#  restriction provided that this copyright statement is not    //
#  removed from the file and that any derivative work contains  //
#  the original copyright notice and the associated disclaimer. //
#                                                               //
#  This source file is free software; you can redistribute it   //
#  and/or modify it under the terms of the GNU Lesser General   //
#  Public License as published by the Free Software Foundation; //
#  either version 2.1 of the License, or (at your option) any   //
#  later version.                                               //
#                                                               //
#  This source is distributed in the hope that it will be       //
#  useful, but WITHOUT ANY WARRANTY; without even the implied   //
#  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
#  PURPOSE.  See the GNU Lesser General Public License for more //
#  details.                                                     //
#                                                               //
#  You should have received a copy of the GNU Lesser General    //
#  Public License along with this source; if not, download it   //
#  from http://www.opencores.org/lgpl.shtml                     //
#                                                               //
# ----------------------------------------------------------------
 
# System
verilog work ../../vlog/system/boot_mem32.v
verilog work ../../vlog/system/boot_mem128.v
verilog work ../../vlog/system/clocks_resets.v
verilog work ../../vlog/system/interrupt_controller.v
verilog work ../../vlog/system/system.v
verilog work ../../vlog/system/test_module.v
verilog work ../../vlog/system/timer_module.v
verilog work ../../vlog/system/uart.v
verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v
verilog work ../../vlog/system/wishbone_arbiter.v
verilog work ../../vlog/system/afifo.v
verilog work ../../vlog/system/ddr3_afifo.v
verilog work ../../vlog/system/ethmac_wb.v
 
# EthMac
verilog work ../../vlog/ethmac/eth_clockgen.v
verilog work ../../vlog/ethmac/eth_crc.v
verilog work ../../vlog/ethmac/eth_fifo.v
verilog work ../../vlog/ethmac/eth_maccontrol.v
verilog work ../../vlog/ethmac/eth_macstatus.v
verilog work ../../vlog/ethmac/eth_miim.v
verilog work ../../vlog/ethmac/eth_outputcontrol.v
verilog work ../../vlog/ethmac/eth_random.v
verilog work ../../vlog/ethmac/eth_receivecontrol.v
verilog work ../../vlog/ethmac/eth_registers.v
verilog work ../../vlog/ethmac/eth_register.v
verilog work ../../vlog/ethmac/eth_rxaddrcheck.v
verilog work ../../vlog/ethmac/eth_rxcounters.v
verilog work ../../vlog/ethmac/eth_rxethmac.v
verilog work ../../vlog/ethmac/eth_rxstatem.v
verilog work ../../vlog/ethmac/eth_shiftreg.v
verilog work ../../vlog/ethmac/eth_spram_256x32.v
verilog work ../../vlog/ethmac/eth_top.v
verilog work ../../vlog/ethmac/eth_transmitcontrol.v
verilog work ../../vlog/ethmac/eth_txcounters.v
verilog work ../../vlog/ethmac/eth_txethmac.v
verilog work ../../vlog/ethmac/eth_txstatem.v
verilog work ../../vlog/ethmac/eth_wishbone.v
verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v
 
# Amber 23
verilog work ../../vlog/amber23/a23_alu.v
verilog work ../../vlog/amber23/a23_barrel_shift.v
verilog work ../../vlog/amber23/a23_barrel_shift_fpga.v
verilog work ../../vlog/amber23/a23_cache.v
verilog work ../../vlog/amber23/a23_coprocessor.v
verilog work ../../vlog/amber23/a23_core.v
verilog work ../../vlog/amber23/a23_decode.v
verilog work ../../vlog/amber23/a23_execute.v
verilog work ../../vlog/amber23/a23_fetch.v
verilog work ../../vlog/amber23/a23_multiply.v
verilog work ../../vlog/amber23/a23_register_bank.v
verilog work ../../vlog/amber23/a23_ram_register_bank.v
verilog work ../../vlog/amber23/a23_wishbone.v
 
# Amber 25
verilog work ../../vlog/amber25/a25_alu.v
verilog work ../../vlog/amber25/a25_barrel_shift.v
verilog work ../../vlog/amber25/a25_shifter.v
verilog work ../../vlog/amber25/a25_coprocessor.v
verilog work ../../vlog/amber25/a25_core.v
verilog work ../../vlog/amber25/a25_dcache.v
verilog work ../../vlog/amber25/a25_decode.v
verilog work ../../vlog/amber25/a25_execute.v
verilog work ../../vlog/amber25/a25_fetch.v
verilog work ../../vlog/amber25/a25_icache.v
verilog work ../../vlog/amber25/a25_mem.v
verilog work ../../vlog/amber25/a25_multiply.v
verilog work ../../vlog/amber25/a25_register_bank.v
verilog work ../../vlog/amber25/a25_wishbone.v
verilog work ../../vlog/amber25/a25_wishbone_buf.v
verilog work ../../vlog/amber25/a25_write_back.v
 
# Xilinx Spartan-6 FPGA Hardware wrappers
verilog work ../../vlog/lib/xs6_addsub_n.v
verilog work ../../vlog/lib/xs6_sram_4096x32_byte_en.v
verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v
verilog work ../../vlog/lib/xs6_sram_512x128_byte_en.v
verilog work ../../vlog/lib/xs6_sram_1024x128_byte_en.v
 
# Xilinx Spartan-6 DDR3 I/F
verilog work ../../vlog/xs6_ddr3/ddr3.v
verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v
verilog work ../../vlog/xs6_ddr3/mcb_ui_top.v
verilog work ../../vlog/xs6_ddr3/infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc_wrapper.v

Line No.	Rev	Author	Line
1	2	csantifort	`# ----------------------------------------------------------------`
2			`# //`
3	23	csantifort	`# Xilinx Spartan-6 FPGA synthesis Verilog source file list //`
4	2	csantifort	`# //`
5			`# This file is part of the Amber project //`
6			`# http://www.opencores.org/project,amber //`
7			`# //`
8			`# Description //`
9			`# //`
10			`# Author(s): //`
11			`# - Conor Santifort, csantifort.amber@gmail.com //`
12			`# //`
13			`#/ ///////////////////////////////////////////////////////////////`
14			`# //`
15			`# Copyright (C) 2010 Authors and OPENCORES.ORG //`
16			`# //`
17			`# This source file may be used and distributed without //`
18			`# restriction provided that this copyright statement is not //`
19			`# removed from the file and that any derivative work contains //`
20			`# the original copyright notice and the associated disclaimer. //`
21			`# //`
22			`# This source file is free software; you can redistribute it //`
23			`# and/or modify it under the terms of the GNU Lesser General //`
24			`# Public License as published by the Free Software Foundation; //`
25			`# either version 2.1 of the License, or (at your option) any //`
26			`# later version. //`
27			`# //`
28			`# This source is distributed in the hope that it will be //`
29			`# useful, but WITHOUT ANY WARRANTY; without even the implied //`
30			`# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
31			`# PURPOSE. See the GNU Lesser General Public License for more //`
32			`# details. //`
33			`# //`
34			`# You should have received a copy of the GNU Lesser General //`
35			`# Public License along with this source; if not, download it //`
36			`# from http://www.opencores.org/lgpl.shtml //`
37			`# //`
38			`# ----------------------------------------------------------------`
39
40			`# System`
41	36	csantifort	`verilog work ../../vlog/system/boot_mem32.v`
42			`verilog work ../../vlog/system/boot_mem128.v`
43	2	csantifort	`verilog work ../../vlog/system/clocks_resets.v`
44			`verilog work ../../vlog/system/interrupt_controller.v`
45			`verilog work ../../vlog/system/system.v`
46			`verilog work ../../vlog/system/test_module.v`
47			`verilog work ../../vlog/system/timer_module.v`
48			`verilog work ../../vlog/system/uart.v`
49			`verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v`
50			`verilog work ../../vlog/system/wishbone_arbiter.v`
51			`verilog work ../../vlog/system/afifo.v`
52			`verilog work ../../vlog/system/ddr3_afifo.v`
53	35	csantifort	`verilog work ../../vlog/system/ethmac_wb.v`
54	2	csantifort
55			`# EthMac`
56			`verilog work ../../vlog/ethmac/eth_clockgen.v`
57			`verilog work ../../vlog/ethmac/eth_crc.v`
58			`verilog work ../../vlog/ethmac/eth_fifo.v`
59			`verilog work ../../vlog/ethmac/eth_maccontrol.v`
60			`verilog work ../../vlog/ethmac/eth_macstatus.v`
61			`verilog work ../../vlog/ethmac/eth_miim.v`
62			`verilog work ../../vlog/ethmac/eth_outputcontrol.v`
63			`verilog work ../../vlog/ethmac/eth_random.v`
64			`verilog work ../../vlog/ethmac/eth_receivecontrol.v`
65			`verilog work ../../vlog/ethmac/eth_registers.v`
66			`verilog work ../../vlog/ethmac/eth_register.v`
67			`verilog work ../../vlog/ethmac/eth_rxaddrcheck.v`
68			`verilog work ../../vlog/ethmac/eth_rxcounters.v`
69			`verilog work ../../vlog/ethmac/eth_rxethmac.v`
70			`verilog work ../../vlog/ethmac/eth_rxstatem.v`
71			`verilog work ../../vlog/ethmac/eth_shiftreg.v`
72			`verilog work ../../vlog/ethmac/eth_spram_256x32.v`
73			`verilog work ../../vlog/ethmac/eth_top.v`
74			`verilog work ../../vlog/ethmac/eth_transmitcontrol.v`
75			`verilog work ../../vlog/ethmac/eth_txcounters.v`
76			`verilog work ../../vlog/ethmac/eth_txethmac.v`
77			`verilog work ../../vlog/ethmac/eth_txstatem.v`
78			`verilog work ../../vlog/ethmac/eth_wishbone.v`
79			`verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v`
80
81	15	csantifort	`# Amber 23`
82			`verilog work ../../vlog/amber23/a23_alu.v`
83			`verilog work ../../vlog/amber23/a23_barrel_shift.v`
84	77	csantifort	`verilog work ../../vlog/amber23/a23_barrel_shift_fpga.v`
85	15	csantifort	`verilog work ../../vlog/amber23/a23_cache.v`
86			`verilog work ../../vlog/amber23/a23_coprocessor.v`
87			`verilog work ../../vlog/amber23/a23_core.v`
88			`verilog work ../../vlog/amber23/a23_decode.v`
89			`verilog work ../../vlog/amber23/a23_execute.v`
90			`verilog work ../../vlog/amber23/a23_fetch.v`
91			`verilog work ../../vlog/amber23/a23_multiply.v`
92			`verilog work ../../vlog/amber23/a23_register_bank.v`
93	77	csantifort	`verilog work ../../vlog/amber23/a23_ram_register_bank.v`
94	15	csantifort	`verilog work ../../vlog/amber23/a23_wishbone.v`
95	2	csantifort
96	15	csantifort	`# Amber 25`
97			`verilog work ../../vlog/amber25/a25_alu.v`
98			`verilog work ../../vlog/amber25/a25_barrel_shift.v`
99	35	csantifort	`verilog work ../../vlog/amber25/a25_shifter.v`
100	15	csantifort	`verilog work ../../vlog/amber25/a25_coprocessor.v`
101			`verilog work ../../vlog/amber25/a25_core.v`
102			`verilog work ../../vlog/amber25/a25_dcache.v`
103			`verilog work ../../vlog/amber25/a25_decode.v`
104			`verilog work ../../vlog/amber25/a25_execute.v`
105			`verilog work ../../vlog/amber25/a25_fetch.v`
106			`verilog work ../../vlog/amber25/a25_icache.v`
107			`verilog work ../../vlog/amber25/a25_mem.v`
108			`verilog work ../../vlog/amber25/a25_multiply.v`
109			`verilog work ../../vlog/amber25/a25_register_bank.v`
110			`verilog work ../../vlog/amber25/a25_wishbone.v`
111	35	csantifort	`verilog work ../../vlog/amber25/a25_wishbone_buf.v`
112	15	csantifort	`verilog work ../../vlog/amber25/a25_write_back.v`
113
114	2	csantifort	`# Xilinx Spartan-6 FPGA Hardware wrappers`
115			`verilog work ../../vlog/lib/xs6_addsub_n.v`
116	61	csantifort	`verilog work ../../vlog/lib/xs6_sram_4096x32_byte_en.v`
117	2	csantifort	`verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v`
118			`verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v`
119			`verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v`
120	36	csantifort	`verilog work ../../vlog/lib/xs6_sram_512x128_byte_en.v`
121	61	csantifort	`verilog work ../../vlog/lib/xs6_sram_1024x128_byte_en.v`
122	2	csantifort
123			`# Xilinx Spartan-6 DDR3 I/F`
124	64	csantifort	`verilog work ../../vlog/xs6_ddr3/ddr3.v`
125	2	csantifort	`verilog work ../../vlog/xs6_ddr3/iodrp_controller.v`
126			`verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v`
127			`verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v`
128			`verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v`
129			`verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v`
130	64	csantifort	`verilog work ../../vlog/xs6_ddr3/mcb_ui_top.v`
131			`verilog work ../../vlog/xs6_ddr3/infrastructure.v`
132			`verilog work ../../vlog/xs6_ddr3/memc_wrapper.v`

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[/] [amber/] [trunk/] [hw/] [fpga/] [bin/] [xs6_source_files.prj] - Blame information for rev 77