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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Memory configuration and Wishbone address decoding //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// This module provides a set of functions that are used to //
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// decode memory addresses so other modules know if an address //
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// is for example in main memory, or boot memory, or a UART //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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// e.g. 24 for 32MBytes, 26 for 128MBytes
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localparam MAIN_MSB = 26;
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csantifort |
// e.g. 13 for 4k words
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localparam BOOT_MSB = 13;
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2 |
csantifort |
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localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */
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localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */
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localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */
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localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */
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localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */
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localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */
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localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */
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localparam HIBOOT_BASE = 32'h2800_0000; /* Uncachable Boot Memory */
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localparam TEST_BASE = 16'hf000; /* Test Module */
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function in_loboot_mem;
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input [31:0] address;
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begin
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in_loboot_mem = (address >= BOOT_BASE &&
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address < (BOOT_BASE + 2**(BOOT_MSB+1)-1));
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end
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endfunction
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function in_hiboot_mem;
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input [31:0] address;
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begin
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in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);
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end
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endfunction
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function in_boot_mem;
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input [31:0] address;
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begin
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in_boot_mem = in_loboot_mem(address) || in_hiboot_mem(address);
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end
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endfunction
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function in_main_mem;
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input [31:0] address;
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begin
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in_main_mem = (address >= MAIN_BASE &&
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address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) &&
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!in_boot_mem ( address );
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end
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endfunction
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// UART 0 address space
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function in_uart0;
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input [31:0] address;
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begin
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in_uart0 = address [31:16] == AMBER_UART0_BASE;
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end
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endfunction
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// UART 1 address space
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function in_uart1;
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input [31:0] address;
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begin
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in_uart1 = address [31:16] == AMBER_UART1_BASE;
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end
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endfunction
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// Interrupt Controller address space
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function in_ic;
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input [31:0] address;
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begin
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in_ic = address [31:16] == AMBER_IC_BASE;
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end
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endfunction
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// Timer Module address space
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function in_tm;
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input [31:0] address;
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begin
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in_tm = address [31:16] == AMBER_TM_BASE;
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end
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endfunction
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// Test module
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function in_test;
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input [31:0] address;
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begin
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in_test = address [31:16] == TEST_BASE;
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end
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endfunction
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// Ethernet MAC
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function in_ethmac;
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input [31:0] address;
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begin
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in_ethmac = address [31:16] == ETHMAC_BASE;
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end
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endfunction
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// Used in fetch.v and l2cache.v to allow accesses to these addresses
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// to be cached
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function in_cachable_mem;
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input [31:0] address;
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begin
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in_cachable_mem = in_loboot_mem ( address ) ||
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in_main_mem ( address ) ;
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end
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endfunction
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