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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [Integration_test/] [FPGA-kc07/] [src/] [deafult_noc_param] - Blame information for rev 56

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$model = bless( {
                  'noc_param' => {
"TOPOLOGY" => "\"MESH\"",
"T1" => "4",
"T2" => "4",
"T3" => "1",
"V" => "1",
"B" => "4",
"LB" => "B",
"Fpay" => "32",
"ROUTE_NAME" => "\"XY\"",
"PCK_TYPE" => "  \"MULTI_FLIT\"",
"MIN_PCK_SIZE" => "2",
"BYTE_EN" => "0",
"SSA_EN" => "\"NO\"",
"CONGESTION_INDEX" => "3",
"ESCAP_VC_MASK" => "2'b01",
"VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",
"MUX_TYPE" => "\"BINARY\"",
"C" => "0",
"CLASS_SETTING"=> "{V{1'b1}}",
"DEBUG_EN" => "1",
"ADD_PIPREG_AFTER_CROSSBAR" => "1'b0",
"FIRST_ARBITER_EXT_P_EN" => "1",
"SWA_ARBITER_TYPE" => "\"RRA\"",
"WEIGHTw" => "4",
"AVC_ATOMIC_EN" => "0",
"SMART_MAX" => "0",
"SELF_LOOP_EN" => "\"NO\"",
"MAX_PCK_NUM " => " 1000000000",
"MAX_PCK_SIZ " => " 16383" ,
"MAX_SIM_CLKs" => "  1000000000",
"TIMSTMP_FIFO_NUM " => " 16",
"CVw"=> "(C==0)? V : C * V",
"CLASS_SETTING" => "{CVw{1'b1}}",
"CAST_TYPE" => "\"UNICAST\"",
                                 },
 
 
 'parameters_order' => {
'noc_param' =>
[
                                                              'TOPOLOGY',
                                                              'T1',
                                                              'T2',
                                                              'T3',
                                                              'V',
                                                              'B',
                                                              'LB',
                                                              'Fpay',
                                                              'ROUTE_NAME',
                                                              'PCK_TYPE',
                                                              'MIN_PCK_SIZE',
                                                              'BYTE_EN',
                                                              'SSA_EN',
                                                              'SMART_MAX',
                                                              'CONGESTION_INDEX',
                                                              'ESCAP_VC_MASK',
                                                              'VC_REALLOCATION_TYPE',
                                                              'COMBINATION_TYPE',
                                                              'MUX_TYPE',
                                                              'C',
'CLASS_SETTING',
                                                              'DEBUG_EN',
                                                              'ADD_PIPREG_AFTER_CROSSBAR',
                                                              'FIRST_ARBITER_EXT_P_EN',
                                                              'SWA_ARBITER_TYPE',
                                                              'WEIGHTw',
                                                              'SELF_LOOP_EN',
                                                              'AVC_ATOMIC_EN',
"MAX_PCK_NUM " ,
"MAX_PCK_SIZ ",
"MAX_SIM_CLKs",
"TIMSTMP_FIFO_NUM ",
"CVw",
"CAST_TYPE"                                                           ],
 
}
 
                },
);

Line No.	Rev	Author	Line
1	56	alirezamon	`$model = bless( {`
2			`'noc_param' => {`
3			`"TOPOLOGY" => "\"MESH\"",`
4			`"T1" => "4",`
5			`"T2" => "4",`
6			`"T3" => "1",`
7			`"V" => "1",`
8			`"B" => "4",`
9			`"LB" => "B",`
10			`"Fpay" => "32",`
11			`"ROUTE_NAME" => "\"XY\"",`
12			`"PCK_TYPE" => " \"MULTI_FLIT\"",`
13			`"MIN_PCK_SIZE" => "2",`
14			`"BYTE_EN" => "0",`
15			`"SSA_EN" => "\"NO\"",`
16			`"CONGESTION_INDEX" => "3",`
17			`"ESCAP_VC_MASK" => "2'b01",`
18			`"VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",`
19			`"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",`
20			`"MUX_TYPE" => "\"BINARY\"",`
21			`"C" => "0",`
22			`"CLASS_SETTING"=> "{V{1'b1}}",`
23			`"DEBUG_EN" => "1",`
24			`"ADD_PIPREG_AFTER_CROSSBAR" => "1'b0",`
25			`"FIRST_ARBITER_EXT_P_EN" => "1",`
26			`"SWA_ARBITER_TYPE" => "\"RRA\"",`
27			`"WEIGHTw" => "4",`
28			`"AVC_ATOMIC_EN" => "0",`
29			`"SMART_MAX" => "0",`
30			`"SELF_LOOP_EN" => "\"NO\"",`
31			`"MAX_PCK_NUM " => " 1000000000",`
32			`"MAX_PCK_SIZ " => " 16383" ,`
33			`"MAX_SIM_CLKs" => " 1000000000",`
34			`"TIMSTMP_FIFO_NUM " => " 16",`
35			`"CVw"=> "(C==0)? V : C * V",`
36			`"CLASS_SETTING" => "{CVw{1'b1}}",`
37			`"CAST_TYPE" => "\"UNICAST\"",`
38			`},`
39
40
41			`'parameters_order' => {`
42			`'noc_param' =>`
43			`[`
44			`'TOPOLOGY',`
45			`'T1',`
46			`'T2',`
47			`'T3',`
48			`'V',`
49			`'B',`
50			`'LB',`
51			`'Fpay',`
52			`'ROUTE_NAME',`
53			`'PCK_TYPE',`
54			`'MIN_PCK_SIZE',`
55			`'BYTE_EN',`
56			`'SSA_EN',`
57			`'SMART_MAX',`
58			`'CONGESTION_INDEX',`
59			`'ESCAP_VC_MASK',`
60			`'VC_REALLOCATION_TYPE',`
61			`'COMBINATION_TYPE',`
62			`'MUX_TYPE',`
63			`'C',`
64			`'CLASS_SETTING',`
65			`'DEBUG_EN',`
66			`'ADD_PIPREG_AFTER_CROSSBAR',`
67			`'FIRST_ARBITER_EXT_P_EN',`
68			`'SWA_ARBITER_TYPE',`
69			`'WEIGHTw',`
70			`'SELF_LOOP_EN',`
71			`'AVC_ATOMIC_EN',`
72			`"MAX_PCK_NUM " ,`
73			`"MAX_PCK_SIZ ",`
74			`"MAX_SIM_CLKs",`
75			`"TIMSTMP_FIFO_NUM ",`
76			`"CVw",`
77			`"CAST_TYPE" ],`
78
79			`}`
80
81			`},`
82			`);`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [Integration_test/] [FPGA-kc07/] [src/] [deafult_noc_param] - Blame information for rev 56