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alirezamon |
#######################################################################
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## File: ProNoC_jtag_uart.IP
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##
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## Copyright (C) 2014-2019 Alireza Monemi
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##
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## This file is part of ProNoC 1.9.1
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##
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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################################################################################
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$ipgen = bless( {
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'system_h' => '
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#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
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#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
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#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
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#define ${IP}_DATA_RVALID_MSK 0x00008000
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#define ${IP}_DATA_DATA_MSK 0x000000FF
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//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
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void jtag_putchar(char ch);
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char jtag_getchar(void);
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void outbyte(char c); //called in printf();
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char inbyte(void);
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void jtag_putchar(char ch);
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char jtag_getchar(void);
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int jtag_scanstr(char* buf);
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int jtag_scanint(int *num);
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/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////
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#define INCLUDE_${INCLUDE_SIM_PRINTF}
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#ifdef INCLUDE_SIMPLE_PRINTF
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#include "simple-printf/printf.h"
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#endif
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#ifdef INCLUDE_SIMPLE_PRINTF_LONG
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#include "simple-printf/printf.h"
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#endif',
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'ports' => {
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'wb_adr_i' => {
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'adr_i'
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},
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'wb_stb_i' => {
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'type' => 'input',
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'intfc_port' => 'stb_i',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => ''
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},
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'clk' => {
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'intfc_name' => 'plug:clk[0]',
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'range' => '',
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'intfc_port' => 'clk_i',
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'type' => 'input'
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},
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'wb_we_i' => {
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'range' => '',
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'intfc_name' => 'plug:wb_slave[0]',
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'intfc_port' => 'we_i',
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'type' => 'input'
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},
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'wb_dat_o' => {
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'intfc_port' => 'dat_o',
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'type' => 'output',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => 'Dw-1: 0'
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},
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'wb_to_jtag' => {
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'range' => 'WB2Jw-1 : 0',
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'intfc_name' => 'socket:jtag_to_wb[0]',
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'intfc_port' => 'jwb_o',
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'type' => 'output'
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},
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'reset' => {
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'range' => '',
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'intfc_name' => 'plug:reset[0]',
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'intfc_port' => 'reset_i',
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'type' => 'input'
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},
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'wb_ack_o' => {
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'intfc_port' => 'ack_o',
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'type' => 'output',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => ''
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},
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'wb_cyc_i' => {
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'intfc_port' => 'cyc_i',
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'type' => 'input',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => ''
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},
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'jtag_to_wb' => {
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'range' => 'J2WBw-1 : 0',
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'intfc_name' => 'socket:jtag_to_wb[0]',
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'intfc_port' => 'jwb_i',
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'type' => 'input'
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},
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'RxD_wr_sim' => {
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'intfc_port' => 'RxD_wr_sim',
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'type' => 'input',
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'range' => '',
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'intfc_name' => 'socket:RxD_sim[0]'
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},
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'RxD_din_sim' => {
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'intfc_port' => 'RxD_din_sim',
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'type' => 'input',
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'range' => '7:0 ',
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'intfc_name' => 'socket:RxD_sim[0]'
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},
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'RxD_ready_sim' => {
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'type' => 'output',
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'intfc_port' => 'RxD_ready_sim',
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'intfc_name' => 'socket:RxD_sim[0]',
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'range' => ''
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},
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'wb_dat_i' => {
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'intfc_port' => 'dat_i',
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'type' => 'input',
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'range' => 'Dw-1: 0',
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'intfc_name' => 'plug:wb_slave[0]'
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}
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},
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'unused' => {
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'plug:wb_slave[0]' => [
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'tag_i',
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'err_o',
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'cti_i',
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'bte_i',
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'rty_o',
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'sel_i'
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]
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},
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'category' => 'Communication',
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'plugs' => {
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'wb_slave' => {
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'type' => 'num',
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'0' => {
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'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
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'width' => 4,
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'name' => 'wb_slave'
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},
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'value' => 1
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},
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'clk' => {
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'type' => 'num',
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'0' => {
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'name' => 'clk'
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},
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'value' => 1
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},
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'reset' => {
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'0' => {
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'name' => 'reset'
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},
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'type' => 'num',
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'value' => 1
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}
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},
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'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v',
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'parameters' => {
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'JDw' => {
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'type' => 'Fixed',
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'global_param' => 'Parameter',
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'default' => '32',
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'info' => 'Parameter',
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'redefine_param' => 1,
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'content' => ''
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},
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'JINDEXw' => {
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'info' => 'Parameter',
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'default' => '8',
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'content' => '',
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'redefine_param' => 1,
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'global_param' => 'Parameter',
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'type' => 'Fixed'
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},
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'J2WBw' => {
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'type' => 'Fixed',
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'global_param' => 'Parameter',
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'redefine_param' => 1,
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'content' => '',
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'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',
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'info' => undef
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},
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'Dw' => {
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'default' => '32',
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'info' => 'Parameter',
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'redefine_param' => 1,
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'content' => '',
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'type' => 'Fixed',
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'global_param' => 'Localparam'
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},
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'JAw' => {
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'global_param' => 'Parameter',
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'type' => 'Fixed',
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'info' => 'Parameter',
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'default' => '32',
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'content' => '',
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'redefine_param' => 1
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},
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'JSTATUSw' => {
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'global_param' => 'Parameter',
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'type' => 'Fixed',
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'content' => '',
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'redefine_param' => 1,
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'info' => 'Parameter',
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'default' => '8'
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},
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| 213 |
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'INCLUDE_SIM_PRINTF' => {
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'redefine_param' => 0,
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'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG',
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'default' => 'SIMPLE_PRINTF',
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'info' => 'Select source code for printf command:
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"NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code.
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"SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported.
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"SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported.',
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'type' => 'Combo-box',
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'global_param' => 'Don\'t include'
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},
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'Aw' => {
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'type' => 'Fixed',
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'global_param' => 'Localparam',
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'redefine_param' => 1,
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'content' => '',
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'default' => '1',
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| 230 |
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'info' => 'Parameter'
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| 231 |
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},
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| 232 |
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'JTAG_CONNECT' => {
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'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
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'redefine_param' => 1,
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'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
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For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
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'default' => '"XILINX_JTAG_WB"',
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| 239 |
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'global_param' => 'Parameter',
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| 240 |
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'type' => 'Combo-box'
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| 241 |
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},
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| 242 |
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'JTAG_INDEX' => {
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'content' => '',
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| 244 |
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'redefine_param' => 1,
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'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
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'default' => '126-CORE_ID',
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| 247 |
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'global_param' => 'Parameter',
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| 248 |
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'type' => 'Entry'
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| 249 |
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},
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| 250 |
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'BUFF_Aw' => {
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| 251 |
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'global_param' => 'Localparam',
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| 252 |
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'type' => 'Spin-button',
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| 253 |
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'content' => '2,16,1',
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| 254 |
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'redefine_param' => 1,
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| 255 |
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'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
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| 256 |
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'default' => '6'
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| 257 |
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},
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| 258 |
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'SELw' => {
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| 259 |
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'global_param' => 'Localparam',
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| 260 |
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'type' => 'Fixed',
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| 261 |
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'info' => 'Parameter',
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| 262 |
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'default' => '4',
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| 263 |
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'content' => '',
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| 264 |
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'redefine_param' => 1
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| 265 |
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},
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| 266 |
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'JTAG_CHAIN' => {
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| 267 |
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'global_param' => 'Parameter',
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| 268 |
|
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'type' => 'Combo-box',
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| 269 |
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'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
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| 270 |
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4: JTAG runtime memory programmers.
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| 271 |
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3: UART
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| 272 |
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1,2: reserved',
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| 273 |
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'default' => '3',
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| 274 |
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'content' => '1,2,3,4',
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| 275 |
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'redefine_param' => 0
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| 276 |
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},
|
| 277 |
|
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'WB2Jw' => {
|
| 278 |
|
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'content' => '',
|
| 279 |
|
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'redefine_param' => 1,
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| 280 |
|
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'info' => '',
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| 281 |
|
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'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1',
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| 282 |
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'global_param' => 'Parameter',
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| 283 |
|
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'type' => 'Fixed'
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| 284 |
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},
|
| 285 |
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'TAGw' => {
|
| 286 |
|
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'type' => 'Fixed',
|
| 287 |
|
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'global_param' => 'Localparam',
|
| 288 |
|
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'default' => '3',
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| 289 |
|
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'info' => 'Parameter',
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| 290 |
|
|
'redefine_param' => 1,
|
| 291 |
|
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'content' => ''
|
| 292 |
|
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}
|
| 293 |
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},
|
| 294 |
|
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'gui_status' => {
|
| 295 |
|
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'status' => 'ideal',
|
| 296 |
|
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'timeout' => 0
|
| 297 |
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},
|
| 298 |
|
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'ip_name' => 'ProNoC_jtag_uart',
|
| 299 |
|
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'ports_order' => [
|
| 300 |
|
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'clk',
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| 301 |
|
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'reset',
|
| 302 |
|
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'wb_dat_o',
|
| 303 |
|
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'wb_ack_o',
|
| 304 |
|
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'wb_adr_i',
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| 305 |
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'wb_stb_i',
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| 306 |
|
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'wb_cyc_i',
|
| 307 |
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'wb_we_i',
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| 308 |
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'wb_dat_i',
|
| 309 |
|
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'wb_to_jtag',
|
| 310 |
|
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'jtag_to_wb',
|
| 311 |
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'RxD_din_sim',
|
| 312 |
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'RxD_wr_sim',
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| 313 |
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'RxD_ready_sim'
|
| 314 |
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],
|
| 315 |
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'version' => 11,
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| 316 |
|
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'description' => 'A jtag uart module. Controled using Altera Vjtag or Xilinx BSCANE2.',
|
| 317 |
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'parameters_order' => [
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| 318 |
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'Aw',
|
| 319 |
|
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'SELw',
|
| 320 |
|
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'TAGw',
|
| 321 |
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'Dw',
|
| 322 |
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'BUFF_Aw',
|
| 323 |
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'JTAG_INDEX',
|
| 324 |
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'JDw',
|
| 325 |
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'JAw',
|
| 326 |
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'JINDEXw',
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| 327 |
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'JSTATUSw',
|
| 328 |
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'JTAG_CHAIN',
|
| 329 |
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'JTAG_CONNECT',
|
| 330 |
|
|
'J2WBw',
|
| 331 |
|
|
'WB2Jw',
|
| 332 |
|
|
'INCLUDE_SIM_PRINTF'
|
| 333 |
|
|
],
|
| 334 |
|
|
'hdl_files' => [
|
| 335 |
|
|
'/mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v',
|
| 336 |
|
|
'/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v'
|
| 337 |
|
|
],
|
| 338 |
|
|
'sw_files' => [
|
| 339 |
|
|
'/mpsoc/src_processor/src_lib/simple-printf'
|
| 340 |
|
|
],
|
| 341 |
|
|
'sockets' => {
|
| 342 |
|
|
'RxD_sim' => {
|
| 343 |
|
|
'connection_num' => 'single connection',
|
| 344 |
|
|
'value' => 1,
|
| 345 |
|
|
'type' => 'num',
|
| 346 |
|
|
'0' => {
|
| 347 |
|
|
'name' => 'RxD_sim'
|
| 348 |
|
|
}
|
| 349 |
|
|
},
|
| 350 |
|
|
|
| 351 |
|
|
'jtag_to_wb' => {
|
| 352 |
|
|
'value' => 1,
|
| 353 |
|
|
'type' => 'num',
|
| 354 |
|
|
'0' => {
|
| 355 |
|
|
'name' => 'jtag_to_wb'
|
| 356 |
|
|
},
|
| 357 |
|
|
'connection_num' => 'single connection'
|
| 358 |
|
|
}
|
| 359 |
|
|
},
|
| 360 |
|
|
'modules' => {
|
| 361 |
|
|
'uart_dual_port_ram' => {},
|
| 362 |
|
|
'pronoc_jtag_uart' => {}
|
| 363 |
|
|
},
|
| 364 |
|
|
'system_c' => '
|
| 365 |
|
|
void outbyte(char c){jtag_putchar(c);} //called in printf();
|
| 366 |
|
|
|
| 367 |
|
|
char inbyte(){return jtag_getchar();}
|
| 368 |
|
|
|
| 369 |
|
|
void jtag_putchar(char ch){ //print one char from jtag_uart
|
| 370 |
|
|
while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
|
| 371 |
|
|
${IP}_DATA_REG=ch;
|
| 372 |
|
|
}
|
| 373 |
|
|
|
| 374 |
|
|
char jtag_getchar(void){ //get one char from jtag_uart
|
| 375 |
|
|
unsigned int data;
|
| 376 |
|
|
data=${IP}_DATA_REG;
|
| 377 |
|
|
while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
|
| 378 |
|
|
data=${IP}_DATA_REG;
|
| 379 |
|
|
return (data & ${IP}_DATA_DATA_MSK);
|
| 380 |
|
|
}
|
| 381 |
|
|
|
| 382 |
|
|
int jtag_scanstr(char* buf){ //scan string until to buf, return str length
|
| 383 |
|
|
char ch; unsigned int i=0;
|
| 384 |
|
|
while(1){
|
| 385 |
|
|
ch=jtag_getchar();
|
| 386 |
|
|
if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
|
| 387 |
|
|
else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
|
| 388 |
|
|
else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
|
| 389 |
|
|
}
|
| 390 |
|
|
return i;
|
| 391 |
|
|
}
|
| 392 |
|
|
|
| 393 |
|
|
int jtag_scanint(int *num){ //return the scanned integer
|
| 394 |
|
|
unsigned int curr_num,strlen,i=0;
|
| 395 |
|
|
char str[11];
|
| 396 |
|
|
strlen=jtag_scanstr(str); //scan str
|
| 397 |
|
|
if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
|
| 398 |
|
|
*num=0;
|
| 399 |
|
|
for(i=0;i
|
| 400 |
|
|
curr_num=(unsigned int)str[i]-\'0\';
|
| 401 |
|
|
if(curr_num>9); //not integer: do nothing
|
| 402 |
|
|
else *num=*num*10+curr_num; //is integer
|
| 403 |
|
|
}
|
| 404 |
|
|
return 0;
|
| 405 |
|
|
}
|
| 406 |
|
|
|
| 407 |
|
|
#ifdef INCLUDE_SIMPLE_PRINTF
|
| 408 |
|
|
#include "simple-printf/printf.c"
|
| 409 |
|
|
#endif
|
| 410 |
|
|
|
| 411 |
|
|
#ifdef INCLUDE_SIMPLE_PRINTF_LONG
|
| 412 |
|
|
#include "simple-printf/prinf_long.c"
|
| 413 |
|
|
#endif
|
| 414 |
|
|
|
| 415 |
|
|
|
| 416 |
|
|
',
|
| 417 |
|
|
'module_name' => 'pronoc_jtag_uart'
|
| 418 |
|
|
}, 'ip_gen' );
|
