URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
#######################################################################
## File: mor1k_mpsoc.MPSOC
##
## Copyright (C) 2014-2021 Alireza Monemi
##
## This file is part of ProNoC 2.1.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
$mor1k_mpsoc = bless( {
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'compile_pin_pos' => {
'processors_en' => [
6,
0
],
'TOP_reset' => [
0,
0
],
'jtag_debug_reset_in' => [
0,
0
],
'TOP_clk' => [
4,
0
]
},
'MEM2' => {
'width' => '14',
'percent' => '75'
},
'RAM2' => {
'end' => 65536,
'start' => 49152
},
'ROM3' => {
'end' => 49152,
'start' => 0
},
'noc_param' => {
'T2' => '2',
'TOPOLOGY' => '"MESH"',
'SELF_LOOP_EN' => '"NO"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'WEIGHTw' => '4',
'BYTE_EN' => '1',
'SMART_MAX' => '0',
'FIRST_ARBITER_EXT_P_EN' => 1,
'ESCAP_VC_MASK' => '2\'b01',
'PCK_TYPE' => '"MULTI_FLIT"',
'DEBUG_EN' => '0',
'CONGESTION_INDEX' => 3,
'T3' => '1',
'MCAST_ENDP_LIST' => '\'hf',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'T1' => '2',
'MIN_PCK_SIZE' => '2',
'B' => '4',
'MUX_TYPE' => '"BINARY"',
'ROUTE_NAME' => '"XY"',
'CAST_TYPE' => '"UNICAST"',
'SWA_ARBITER_TYPE' => '"RRA"',
'C' => 0,
'Fpay' => '32',
'V' => '2',
'AVC_ATOMIC_EN' => 0,
'LB' => '4',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'SSA_EN' => '"NO"'
},
'compile_assign_type' => {
'processors_en' => 'Direct',
'TOP_clk' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'TOP_reset' => 'Direct'
},
'fpga_param' => {},
'socs' => {
'mor1k_tile' => {
'top' => bless( {
'parameters' => {
'uart_JDw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'uart_JSTATUSw' => '8',
'ram_JAw' => '32'
},
'tiles' => {
'1' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JSTATUSw' => '8',
'uart_JSTATUSw' => '8',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'2' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_Dw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'0' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_Aw' => '14',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'3' => {
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_JINDEXw' => '8'
}
}
},
'instance_ids' => {
'mor1kx0' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'module' => 'mor1kx',
'instance' => 'cpu',
'module_name' => 'mor1k',
'category' => 'Processor',
'localparam' => {
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DIVIDER' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation',
'type' => 'Combo-box',
'default' => '"SERIAL"'
},
'cpu_FEATURE_DMMU' => {
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_MULTIPLIER' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Specify the multiplier implementation',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'type' => 'Combo-box',
'default' => '"THREESTAGE"'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_OPTION_SHIFTER' => {
'type' => 'Combo-box',
'default' => '"BARREL"',
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => '32',
'type' => 'Fixed'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => '',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
}
}
},
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim'
},
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'range' => ''
}
},
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_BUFF_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'type' => 'Spin-button',
'default' => '4'
},
'uart_Aw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '1',
'info' => 'Parameter'
},
'uart_Dw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_SELw' => {
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_TAGw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'parameters' => {
'uart_JSTATUSw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter'
},
'uart_JINDEXw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '8'
},
'uart_JTAG_CONNECT' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JTAG_INDEX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '126-CORE_ID',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'type' => 'Entry',
'content' => ''
},
'uart_J2WBw' => {
'type' => 'Fixed',
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'type' => 'Combo-box',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'content' => ''
},
'uart_JAw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
}
},
'single_port_ram0' => {
'localparam' => {
'ram_BYTE_WR_EN' => {
'default' => '"YES"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'content' => '',
'info' => 'Parameter'
},
'ram_INIT_FILE_PATH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => 'SW_LOC',
'type' => 'Fixed'
},
'ram_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"',
'content' => '"YES","NO"',
'type' => 'Combo-box'
},
'ram_CTIw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '3'
},
'ram_CORE_NUM' => {
'content' => '',
'info' => 'Parameter',
'default' => 'CORE_ID',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_WB_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'content' => '4,31,1',
'type' => 'Spin-button',
'default' => '20'
},
'ram_SELw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => ''
},
'ram_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Memory address width',
'content' => '4,31,1',
'default' => '14',
'type' => 'Spin-button'
},
'ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ALTERA"',
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => ''
},
'ram_BTEw' => {
'info' => 'Parameter',
'content' => '',
'default' => '2',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'type' => 'Entry',
'content' => ''
}
},
'parameters' => {
'ram_JSTATUSw' => {
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JAw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"ALTERA_JTAG_WB"'
},
'ram_Dw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'type' => 'Spin-button',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'content' => ''
},
'ram_J2WBw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'ram_JDw' => {
'info' => 'Parameter',
'content' => '',
'default' => 'ram_Dw',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'default' => 'CORE_ID',
'type' => 'Entry',
'content' => '',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'ports' => {
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input'
}
},
'module' => 'single_port_ram',
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'category' => 'RAM'
},
'clk_source0' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'source_reset_in' => {
'range' => '',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
}
},
'localparam' => {
'source_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'clk_source',
'instance' => 'source',
'module_name' => 'clk_source',
'category' => 'Source'
},
'ni_master0' => {
'localparam' => {
'ni_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'default' => '"NO"',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed'
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'type' => 'Combo-box'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'type' => 'Spin-button',
'default' => '13'
},
'ni_M_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'content' => 'Dw',
'info' => 'Parameter'
},
'ni_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'type' => 'Spin-button',
'content' => '32,256,8'
},
'ni_S_Aw' => {
'default' => '8',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_HDATA_PRECAPw' => {
'default' => '0',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '0,8,1'
}
},
'parameters' => {
'ni_EAw' => {
'redefine_param' => 0,
'global_param' => 'Parameter',
'info' => undef,
'content' => '',
'default' => '16',
'type' => 'Fixed'
},
'ni_RAw' => {
'type' => 'Fixed',
'default' => '16',
'content' => '',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 0
}
},
'module' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_chan_in' => {
'type' => 'input',
'intfc_port' => 'chan_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'chan_out'
}
},
'module_name' => 'ni_master',
'category' => 'NoC'
},
'timer0' => {
'category' => 'Timer',
'module_name' => 'timer',
'module' => 'timer',
'instance' => 'timer',
'localparam' => {
'timer_Aw' => {
'default' => '3',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed'
},
'timer_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => '4',
'type' => 'Fixed'
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
',
'default' => '8',
'content' => '1,32,1',
'type' => 'Spin-button'
},
'timer_TAGw' => {
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'localparam' => {
'bus_S' => {
'content' => '1,256,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Number of wishbone slave interface',
'default' => '4'
},
'bus_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => 'bus_Dw/8',
'content' => '',
'type' => 'Fixed'
},
'bus_Aw' => {
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '3',
'content' => '',
'type' => 'Fixed'
},
'bus_M' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'content' => '1,256,1'
},
'bus_BTEw' => {
'default' => '2 ',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'bus_CTIw' => {
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_Dw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'type' => 'Spin-button'
}
},
'instance' => 'bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus'
}
},
'interface' => {
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0'
},
'uart_RxD_ready_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'uart_RxD_wr_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'type' => 'input',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
}
}
}
},
'ports' => {
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0'
},
'source_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => ''
},
'uart_jtag_to_wb' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'source_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_out' => {
'type' => 'output',
'intfc_port' => 'chan_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t'
}
}
}, 'ip_gen' ),
'tile_nums' => [
0,
1,
2,
3
]
}
},
'MEM1' => {
'width' => '14',
'percent' => '75'
},
'ROM0' => {
'start' => 0,
'end' => 22937
},
'file_name' => undef,
'RAM1' => {
'end' => 65536,
'start' => 49152
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'SOURCE_SET_CONNECT' => {
'T3_cs_clk_in' => 'clk',
'T0_cs_reset_in' => 'reset',
'T3_ss_clk_in' => 'clk0',
'T0_ss_reset_in' => 'reset0',
'NoC_reset' => 'reset',
'T1_ss_reset_in' => 'reset0',
'T2_ss_reset_in' => 'reset0',
'T1_cs_reset_in' => 'reset',
'T2_cs_reset_in' => 'reset',
'T2_ss_clk_in' => 'clk0',
'T1_ss_clk_in' => 'clk0',
'T2_cs_clk_in' => 'clk',
'T1_cs_clk_in' => 'clk',
'T0_cs_clk_in' => 'clk',
'T3_cs_reset_in' => 'reset',
'T0_ss_clk_in' => 'clk0',
'T3_ss_reset_in' => 'reset0',
'NoC_clk' => 'clk'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'get_config_adj' => {
'ha' => '0',
'va' => '0'
},
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'compile_pin' => {
'jtag_debug_reset_in' => '*GND',
'TOP_reset' => '*GND',
'TOP_clk' => 'FPGA_CLK1_50',
'processors_en' => 'KEY'
},
'RAM0' => {
'start' => 22937,
'end' => 32768
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'compile_pin_range_lsb' => {
'processors_en' => 0
},
'compile' => {
'type' => 'Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'cpu_num' => '4',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
},
'tile' => {
'0' => {},
'2' => {},
'1' => {},
'3' => {}
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'SOURCE_SET' => {
'reset_0_name' => 'reset',
'clk_number' => 1,
'reset_number' => 1,
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'TOP' => {
'version' => 0
},
'hdl_files' => undef,
'instance_order' => [
'TOP'
],
'instances' => {
'TOP' => {
'module_name' => 'TOP',
'category' => 'TOP',
'plugs' => {
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'clk',
'connect_socket' => undef
}
},
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'reset'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'description_pdf' => undef,
'instance_name' => 'TOP',
'parameters_order' => [],
'module' => 'TOP',
'sockets' => {}
}
},
'modules' => {},
'soc_name' => {
'TOP' => undef
},
'SOURCE_SET' => {
'IP' => bless( {
'ip_name' => 'TOP',
'ports_order' => [],
'ports' => {
'reset' => {
'range' => undef,
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => undef
}
},
'file_name' => undef,
'hdl_files_ticked' => [],
'parameters_order' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'module_name' => 'TOP',
'category' => 'TOP',
'hdl_files' => [],
'plugs' => {
'reset' => {
'1' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'clk' => {
'1' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'clk'
}
}
}
}, 'ip_gen' )
},
'device_win_adj' => {
'va' => '0',
'ha' => '0'
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
}
}, 'soc' )
},
'noc_indept_param' => {},
'verilator' => {
'libs' => {
'Vtile1' => '--top-module tile_1',
'Vtile3' => '--top-module tile_3',
'Vtile0' => '--top-module tile_0',
'Vrouter1' => '--top-module router_top_v -GP=5 ',
'Vtile2' => '--top-module tile_2'
}
},
'soc_param' => {
'default' => {
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_JSTATUSw' => '8',
'ram_Dw' => '32',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JINDEXw' => '8'
}
},
'current_tile_param' => undef,
'compile_pin_range_hsb' => {},
'mpsoc_name' => 'mor1k_mpsoc',
'gen_tiles_adj' => {
'va' => '0',
'ha' => '0'
},
'setting' => {
'show_noc_setting' => 1,
'show_adv_setting' => 0,
'show_tile_setting' => 1,
'soc_path' => 'lib/soc'
},
'top_ip' => bless( {
'ports' => {
'T1_uart_jtag_to_wb' => {
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'instance_name' => 'T3',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T2_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'clk' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'IO'
},
'T3_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'IO'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'IO',
'range' => ''
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_WB2Jw-1 : 0',
'instance_name' => 'T2'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T3',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T3_uart_jtag_to_wb' => {
'instance_name' => 'T3',
'range' => 'T3_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T1_ram_wb_to_jtag' => {
'range' => 'T1_ram_WB2Jw-1 : 0',
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T0_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'instance_name' => 'T0'
},
'T2_uart_wb_to_jtag' => {
'range' => 'T2_uart_WB2Jw-1 : 0',
'instance_name' => 'T2',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
},
'interface' => {
'socket:jtag_to_wb[0]' => {
'ports' => {
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T3_uart_wb_to_jtag' => {
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_uart_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T3',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T1_uart_jtag_to_wb' => {
'range' => 'T1_uart_J2WBw-1 : 0',
'instance_name' => 'T1',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T2_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T2_uart_wb_to_jtag' => {
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T0_ram_WB2Jw-1 : 0',
'instance_name' => 'T0'
},
'T1_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_ram_WB2Jw-1 : 0',
'instance_name' => 'T2'
},
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T1_ram_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_uart_J2WBw-1 : 0',
'instance_name' => 'T3'
}
}
},
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'instance_name' => 'IO',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'plug:clk[0]' => {
'ports' => {
'clk' => {
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'IO',
'range' => ''
}
}
}
},
'instance_ids' => {
'T2' => {
'ports' => {
'T2_ram_wb_to_jtag' => {
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T2_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T2_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_J2WBw-1 : 0'
}
}
},
'IO' => {
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => ''
},
'processors_en' => {
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]'
},
'clk' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]'
}
}
},
'T1' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'T1_uart_J2WBw-1 : 0'
}
}
},
'T0' => {
'ports' => {
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T0_ram_WB2Jw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T0_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'range' => 'T0_uart_WB2Jw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_J2WBw-1 : 0'
}
}
},
'T3' => {
'ports' => {
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
}
}
}
}
}, 'ip_gen' ),
'JTAG' => {
'M_CHAIN' => 4
},
'parameters_order' => {
'compile' => [
'cpu_num'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
],
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'LB',
'PCK_TYPE',
'CAST_TYPE',
'SMART_MAX',
'SELF_LOOP_EN',
'MCAST_ENDP_LIST'
],
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
]
},
'liststore' => {
'va' => '0',
'ha' => '0'
}
}, 'mpsoc' );
