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/************************************************************************** ** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE ** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification. ****************************************************************************/ /********************************************************************** ** File: xilinx_test_mp.v ** ** Copyright (C) 2014-2019 Alireza Monemi ** ** This file is part of ProNoC 1.9.1 ** ** ProNoC ( stands for Prototype Network-on-chip) is free software: ** you can redistribute it and/or modify it under the terms of the GNU ** Lesser General Public License as published by the Free Software Foundation, ** either version 2 of the License, or (at your option) any later version. ** ** ProNoC is distributed in the hope that it will be useful, but WITHOUT ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General ** Public License for more details. ** ** You should have received a copy of the GNU Lesser General Public ** License along with ProNoC. If not, see . ******************************************************************************/ module soc #( parameter CORE_ID=0, parameter SW_LOC="target_dir/sw1" )( MP_T0_led_port_o, MP_T0_ram_jtag_to_wb, MP_T0_ram_wb_to_jtag, MP_T1_led_port_o, MP_T1_ram_jtag_to_wb, MP_T1_ram_wb_to_jtag, MP_T2_led_port_o, MP_T2_ram_jtag_to_wb, MP_T2_ram_wb_to_jtag, MP_T3_led_port_o, MP_T3_ram_jtag_to_wb, MP_T3_ram_wb_to_jtag, MP_enable0, pll_clk_in, pll_reset_in ); function integer log2; input integer number; begin log2=0; while(2**log2

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [verilog/] [xilinx_test_mp.v] - Blame information for rev 48

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