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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_modelsim/] [pck_injector_test.sv] - Blame information for rev 56

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// synthesis translate_off
`include "pronoc_def.v"
 
module pck_injector_test;
        parameter NOC_ID=0;
    `NOC_CONF
 
        reg     reset ,clk;
 
        initial begin
                clk = 1'b0;
                forever clk = #10 ~clk;
        end
 
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
        smartflit_chanel_t chan_out_all [NE-1 : 0];
 
        pck_injct_t pck_injct_in [NE-1 : 0];
        pck_injct_t pck_injct_out[NE-1 : 0];
 
 
        noc_top  # (
                .NOC_ID(NOC_ID)
        ) the_noc (
                .reset(reset),
                .clk(clk),
                .chan_in_all(chan_in_all),
                .chan_out_all(chan_out_all),
                .router_event( )
        );
 
        reg  [NEw-1 : 0] dest_id [NE-1 : 0];
        wire [NEw-1 : 0] src_id  [NE-1 : 0];
        wire [NEw-1: 0] current_e_addr [NE-1 : 0];
 
        genvar i;
        generate
        for(i=0; i< NE; i=i+1) begin : endpoints
 
                endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
 
                packet_injector #(
                        .NOC_ID(NOC_ID)
                ) pck_inj (
                        //general
                        .current_e_addr(current_e_addr[i]),
                        .reset(reset),
                        .clk(clk),
                        //noc port
                        .chan_in(chan_out_all[i]),
                        .chan_out(chan_in_all[i]),
                        //control interafce
                        .pck_injct_in(pck_injct_in[i]),
                        .pck_injct_out(pck_injct_out[i])
                );
 
 
                endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));
 
 
           reg [31:0]k;
 
                initial begin
`ifdef ACTIVE_LOW_RESET_MODE
        reset = 1'b0;
 `else
        reset = 1'b1;
`endif
                        k=0;
                        pck_injct_in[i].data =0;
                        #10
                        pck_injct_in[i].class_num=0;
                        pck_injct_in[i].init_weight=1;
                        pck_injct_in[i].vc=1;
                        pck_injct_in[i].pck_wr=1'b0;
                        #100
                        @(posedge clk) #1;
                        reset=~reset;
                        #100
                        @(posedge clk) #1;
                        if(i==1) begin
                                repeat(10) begin
                                        while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
 
                                        pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
                                        pck_injct_in[i].size=3+(k%18);
                                        dest_id[i]=0;
                                        pck_injct_in[i].pck_wr=1'b1;
                                        @(posedge clk)  #1 k++;
                                        pck_injct_in[i].pck_wr=1'b0;
                                        @(posedge clk)  #1 k++;
 
                                end
 
                                #8000
                        @(posedge clk) $stop;
 
                        end
 
 
 
 
 
 
                end
 
                endp_addr_decoder  #(   .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decode1 ( .id(src_id[i]), .code(pck_injct_out[i].endp_addr));
 
                always @(posedge clk) begin
                        if(pck_injct_out[i].pck_wr) begin
                                $display ("%t:pck_inj(%d) got a packet from source_id=%d, with size=%d flits and data=%h",$time,i,
                                                src_id[i],pck_injct_out[i].size,pck_injct_out[i].data);
                        end
 
                end
 
 
 
        end//for
        endgenerate
 
 
 
 
 
 
 
 
 
 
 
endmodule
// synthesis translate_on
 

Line No.	Rev	Author	Line
1	48	alirezamon	`// synthesis translate_off`
2	56	alirezamon	`include "pronoc_def.v"
3	48	alirezamon
4			`module pck_injector_test;`
5	56	alirezamon	`parameter NOC_ID=0;`
6			`NOC_CONF
7	48	alirezamon
8			`reg reset ,clk;`
9
10			`initial begin`
11			`clk = 1'b0;`
12			`forever clk = #10 ~clk;`
13			`end`
14
15			`smartflit_chanel_t chan_in_all [NE-1 : 0];`
16			`smartflit_chanel_t chan_out_all [NE-1 : 0];`
17
18			`pck_injct_t pck_injct_in [NE-1 : 0];`
19			`pck_injct_t pck_injct_out[NE-1 : 0];`
20
21
22	56	alirezamon	`noc_top # (`
23			`.NOC_ID(NOC_ID)`
24			`) the_noc (`
25	48	alirezamon	`.reset(reset),`
26			`.clk(clk),`
27			`.chan_in_all(chan_in_all),`
28	54	alirezamon	`.chan_out_all(chan_out_all),`
29			`.router_event( )`
30	48	alirezamon	`);`
31
32	56	alirezamon	`reg [NEw-1 : 0] dest_id [NE-1 : 0];`
33			`wire [NEw-1 : 0] src_id [NE-1 : 0];`
34	48	alirezamon	`wire [NEw-1: 0] current_e_addr [NE-1 : 0];`
35
36			`genvar i;`
37			`generate`
38			`for(i=0; i< NE; i=i+1) begin : endpoints`
39
40			`endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));`
41
42	56	alirezamon	`packet_injector #(`
43			`.NOC_ID(NOC_ID)`
44			`) pck_inj (`
45	48	alirezamon	`//general`
46			`.current_e_addr(current_e_addr[i]),`
47			`.reset(reset),`
48			`.clk(clk),`
49			`//noc port`
50			`.chan_in(chan_out_all[i]),`
51			`.chan_out(chan_in_all[i]),`
52			`//control interafce`
53			`.pck_injct_in(pck_injct_in[i]),`
54			`.pck_injct_out(pck_injct_out[i])`
55			`);`
56
57
58			`endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));`
59
60
61			`reg [31:0]k;`
62
63			`initial begin`
64	56	alirezamon	`ifdef ACTIVE_LOW_RESET_MODE
65			`reset = 1'b0;`
66			`else
67			`reset = 1'b1;`
68			`endif
69	48	alirezamon	`k=0;`
70			`pck_injct_in[i].data =0;`
71			`#10`
72			`pck_injct_in[i].class_num=0;`
73			`pck_injct_in[i].init_weight=1;`
74			`pck_injct_in[i].vc=1;`
75			`pck_injct_in[i].pck_wr=1'b0;`
76			`#100`
77			`@(posedge clk) #1;`
78	56	alirezamon	`reset=~reset;`
79	48	alirezamon	`#100`
80			`@(posedge clk) #1;`
81			`if(i==1) begin`
82			`repeat(10) begin`
83			`while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk) #1;`
84
85			`pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;`
86			`pck_injct_in[i].size=3+(k%18);`
87			`dest_id[i]=0;`
88			`pck_injct_in[i].pck_wr=1'b1;`
89			`@(posedge clk) #1 k++;`
90			`pck_injct_in[i].pck_wr=1'b0;`
91			`@(posedge clk) #1 k++;`
92
93			`end`
94
95			`#8000`
96			`@(posedge clk) $stop;`
97
98			`end`
99
100
101
102
103
104
105			`end`
106
107	56	alirezamon	`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decode1 ( .id(src_id[i]), .code(pck_injct_out[i].endp_addr));`
108
109	48	alirezamon	`always @(posedge clk) begin`
110			`if(pck_injct_out[i].pck_wr) begin`
111	56	alirezamon	`$display ("%t:pck_inj(%d) got a packet from source_id=%d, with size=%d flits and data=%h",$time,i,`
112			`src_id[i],pck_injct_out[i].size,pck_injct_out[i].data);`
113	48	alirezamon	`end`
114
115			`end`
116
117
118
119			`end//for`
120			`endgenerate`
121
122
123
124
125
126
127
128
129
130
131
132			`endmodule`
133			`// synthesis translate_on`
134

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_modelsim/] [pck_injector_test.sv] - Blame information for rev 56