URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
/**************************************
* Module: fattree
* Date:2019-01-01
* Author: alireza
*
*
Description:
FatTree
Each level of the hierarchical indirect Network has
k^(l-1) Routers. The Routers are organized such that
each node has k descendents, and each parent is
replicated k times.
most routers has 2K ports, excep the top level has only K
***************************************/
module fattree_noc_top
import pronoc_pkg::*;
(
reset,
clk,
chan_in_all,
chan_out_all
);
input clk,reset;
//local ports
input smartflit_chanel_t chan_in_all [NE-1 : 0];
output smartflit_chanel_t chan_out_all [NE-1 : 0];
//all routers port
smartflit_chanel_t router_chan_in [NR-1 :0][MAX_P-1 : 0];
smartflit_chanel_t router_chan_out [NR-1 :0][MAX_P-1 : 0];
localparam
PV = V * MAX_P,
PFw = MAX_P * Fw,
NRL= NE/K, //number of router in each layer
NEFw = NE * Fw,
NEV = NE * V,
CONG_ALw = CONGw * MAX_P,
PLKw = MAX_P * LKw,
PLw = MAX_P * Lw,
PRAw = MAX_P * RAw; // {layer , Pos} width
function integer addrencode;
input integer pos,k,n,kw;
integer pow,i,tmp;begin
addrencode=0;
pow=1;
for (i = 0; i
