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alirezamon |
`include "pronoc_def.v"
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48 |
alirezamon |
//`define MONITORE_PATH
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/**********************************************************************
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** File: input_ports.sv
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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** This file is part of ProNoC
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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**
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**
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** Description:
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** NoC router input Port. It consists of input buffer, control FIFO
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** and request masking/generation control modules
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**
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**************************************************************/
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56 |
alirezamon |
module input_ports #(
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parameter NOC_ID=0,
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parameter P=5
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) (
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current_r_addr,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted_all,
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flit_in_all,
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flit_in_wr_all,
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reset_ivc_all,
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flit_is_tail_all,
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ivc_request_all,
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dest_port_all,
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flit_out_all,
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assigned_ovc_not_full_all,
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ovc_is_assigned_all,
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sel,
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port_pre_sel,
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swap_port_presel,
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nonspec_first_arbiter_granted_ivc_all,
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credit_out_all,
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destport_clear,
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vc_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_all,
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oports_weight_all,
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granted_dest_port_all,
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refresh_w_counter,
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ivc_info,
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vsa_ctrl_in,
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ssa_ctrl_in,
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smart_ctrl_in,
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credit_init_val_out,
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reset,
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clk
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);
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`NOC_CONF
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48 |
alirezamon |
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localparam
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PV = V * P,
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VV = V * V,
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PVV = PV * V,
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P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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PP_1 = P * P_1,
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VP_1 = V * P_1,
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PVP_1 = PV * P_1,
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PFw = P*Fw,
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W= WEIGHTw,
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WP= W * P,
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WPP = WP * P,
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PVDSTPw= PV * DSTPw,
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alirezamon |
PRAw= P * RAw;
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48 |
alirezamon |
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input reset,clk;
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input [RAw-1 : 0] current_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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output [PV-1 : 0] ivc_num_getting_sw_grant;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [PFw-1 : 0] flit_in_all;
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input [P-1 : 0] flit_in_wr_all;
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output [PV-1 : 0] reset_ivc_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] ivc_request_all;
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alirezamon |
output [PV-1 : 0] credit_out_all;
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alirezamon |
output [PVP_1-1 : 0] dest_port_all;
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output [PFw-1 : 0] flit_out_all;
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54 |
alirezamon |
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48 |
alirezamon |
input [PV-1 : 0] assigned_ovc_not_full_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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input [PV-1 : 0] sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [PV-1 : 0] swap_port_presel;
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56 |
alirezamon |
input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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48 |
alirezamon |
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output [WP-1 : 0] iport_weight_all;
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output [PV-1 : 0] vc_weight_is_consumed_all;
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output [P-1 : 0] iport_weight_is_consumed_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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56 |
alirezamon |
output [WPP-1 : 0] oports_weight_all;
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54 |
alirezamon |
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48 |
alirezamon |
output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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input refresh_w_counter;
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54 |
alirezamon |
input [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
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48 |
alirezamon |
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genvar i;
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generate
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56 |
alirezamon |
for(i=0;i
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48 |
alirezamon |
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input_queue_per_port
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// iport_reg_base
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56 |
alirezamon |
#(
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.NOC_ID(NOC_ID),
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.SW_LOC(i),
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.P(P)
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) the_input_queue_per_port (
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.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
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.current_r_addr(current_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
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.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
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.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
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.flit_in_wr(flit_in_wr_all[i]),
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.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
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.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
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.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
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.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
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.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
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.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
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.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
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.sel(sel [(i+1)*V-1 : i*V]),
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.port_pre_sel(port_pre_sel),
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.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
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.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
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.reset(reset),
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.clk(clk),
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.destport_clear(destport_clear [i]),
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.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
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.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
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.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
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.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
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.refresh_w_counter(refresh_w_counter),
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.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
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.ivc_info(ivc_info[i]),
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.vsa_ctrl_in(vsa_ctrl_in [i]),
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.smart_ctrl_in(smart_ctrl_in [i]),
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.ssa_ctrl_in(ssa_ctrl_in [i]),
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.credit_init_val_out(credit_init_val_out[i])
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);
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48 |
alirezamon |
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end//for
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endgenerate
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endmodule
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/**************************
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input_queue_per_port
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**************************/
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56 |
alirezamon |
module input_queue_per_port #(
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parameter NOC_ID=0,
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parameter P = 5, // router port num
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parameter SW_LOC = 0
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) (
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current_r_addr,
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credit_out,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted,
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flit_in,
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flit_in_wr,
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reset_ivc,
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flit_is_tail,
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ivc_request,
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dest_port,
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flit_out,
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assigned_ovc_not_full,
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ovc_is_assigned,
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sel,
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port_pre_sel,
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swap_port_presel,
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reset,
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clk,
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nonspec_first_arbiter_granted_ivc,
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destport_clear,
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iport_weight,
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oports_weight,
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vc_weight_is_consumed,
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iport_weight_is_consumed,
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refresh_w_counter,
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granted_dest_port,
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ivc_info,
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smart_ctrl_in,
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vsa_ctrl_in,
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ssa_ctrl_in,
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credit_init_val_out
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);
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`NOC_CONF
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54 |
alirezamon |
localparam
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PORT_B = port_buffer_size(SW_LOC),
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PORT_Bw= log2(PORT_B);
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| 230 |
56 |
alirezamon |
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48 |
alirezamon |
localparam
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VV = V * V,
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VDSTPw = V * DSTPw,
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W = WEIGHTw,
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WP = W * P,
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P_1=( SELF_LOOP_EN=="NO")? P-1 : P,
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VP_1 = V * P_1;
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localparam
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/* verilator lint_off WIDTH */
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OFFSET = (PORT_B%MIN_PCK_SIZE)? 1 :0,
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NON_ATOM_PCKS = (PORT_B>MIN_PCK_SIZE)? (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
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MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS + OVC_ALLOC_MODE,// min packet size is two hence the max packet number in buffer is (B/2)
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IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN=="YES")| SMART_EN)? "YES" : "NO";
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localparam
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ELw = log2(T3),
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Pw = log2(P),
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PLw = (TOPOLOGY == "FMESH") ? Pw : ELw,
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VPLw= V * PLw,
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PRAw= P * RAw;
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/* verilator lint_on WIDTH */
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| 256 |
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input reset, clk;
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| 257 |
54 |
alirezamon |
output [V-1 : 0] credit_out;
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| 258 |
48 |
alirezamon |
input [RAw-1 : 0] current_r_addr;
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| 259 |
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input [PRAw-1: 0] neighbors_r_addr;
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| 260 |
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output [V-1 : 0] ivc_num_getting_sw_grant;
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| 261 |
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input any_ivc_sw_request_granted;
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input [Fw-1 : 0] flit_in;
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| 263 |
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input flit_in_wr;
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| 264 |
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output [V-1 : 0] reset_ivc;
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| 265 |
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output [V-1 : 0] flit_is_tail;
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output [V-1 : 0] ivc_request;
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| 267 |
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output [VP_1-1 : 0] dest_port;
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| 268 |
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output [Fw-1 : 0] flit_out;
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| 269 |
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input [V-1 : 0] assigned_ovc_not_full;
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| 270 |
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output [V-1 : 0] ovc_is_assigned;
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| 271 |
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input [V-1 : 0] sel;
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| 272 |
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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| 273 |
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| 274 |
54 |
alirezamon |
input [DSTPw-1 : 0] destport_clear [V-1 : 0];
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| 275 |
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output [WEIGHTw-1 : 0] iport_weight;
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| 276 |
48 |
alirezamon |
output [V-1 : 0] vc_weight_is_consumed;
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| 277 |
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output iport_weight_is_consumed;
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| 278 |
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input refresh_w_counter;
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| 279 |
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input [P_1-1 : 0] granted_dest_port;
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| 280 |
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output [WP-1 : 0] oports_weight;
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| 281 |
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input [PPSw-1 : 0] port_pre_sel;
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| 282 |
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input [V-1 : 0] swap_port_presel;
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| 283 |
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| 284 |
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output ivc_info_t ivc_info [V-1 : 0];
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| 285 |
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input smart_ctrl_t smart_ctrl_in;
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| 286 |
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input vsa_ctrl_t vsa_ctrl_in;
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| 287 |
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input ssa_ctrl_t ssa_ctrl_in;
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| 288 |
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output [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
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| 289 |
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| 290 |
54 |
alirezamon |
wire [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
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| 291 |
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//for multicast
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| 292 |
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wire [DSTPw-1 : 0] dest_port_multi [V-1 : 0];
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| 293 |
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wire [V-1 : 0] multiple_dest,dst_onhot0;
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| 294 |
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wire [DSTPw-1 : 0] clear_dspt_mulicast [V-1 : 0];
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| 295 |
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| 296 |
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wire [VV-1 : 0] candidate_ovcs;
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| 297 |
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| 298 |
48 |
alirezamon |
wire [Cw-1 : 0] class_in;
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| 299 |
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wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
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| 300 |
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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| 301 |
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| 302 |
54 |
alirezamon |
wire [DAw-1 : 0] dest_e_addr_in;
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| 303 |
48 |
alirezamon |
wire [EAw-1 : 0] src_e_addr_in;
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| 304 |
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wire [V-1 : 0] vc_num_in;
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| 305 |
|
|
wire [V-1 : 0] hdr_flit_wr,flit_wr;
|
| 306 |
54 |
alirezamon |
wire [VV-1 : 0] assigned_ovc_num;
|
| 307 |
48 |
alirezamon |
|
| 308 |
|
|
wire [DSTPw-1 : 0] lk_destination_in_encoded;
|
| 309 |
|
|
wire [WEIGHTw-1 : 0] weight_in;
|
| 310 |
|
|
wire [Fw-1 : 0] buffer_out;
|
| 311 |
|
|
wire hdr_flg_in,tail_flg_in;
|
| 312 |
|
|
wire [V-1 : 0] ivc_not_empty;
|
| 313 |
|
|
wire [Cw-1 : 0] class_out [V-1 : 0];
|
| 314 |
|
|
wire [VPLw-1 : 0] endp_localp_num;
|
| 315 |
|
|
|
| 316 |
|
|
wire [V-1 : 0] smart_hdr_en;
|
| 317 |
|
|
wire [ELw-1 : 0] endp_l_in;
|
| 318 |
|
|
wire [Pw-1 : 0] endp_p_in;
|
| 319 |
|
|
|
| 320 |
|
|
wire [V-1 : 0] rd_hdr_fwft_fifo,wr_hdr_fwft_fifo,rd_hdr_fwft_fifo_delay,wr_hdr_fwft_fifo_delay;
|
| 321 |
|
|
|
| 322 |
|
|
logic [V-1 : 0] ovc_is_assigned_next;
|
| 323 |
|
|
logic [VV-1 : 0] assigned_ovc_num_next;
|
| 324 |
|
|
|
| 325 |
|
|
wire odd_column = current_r_addr[0];
|
| 326 |
|
|
wire [P-1 : 0] destport_one_hot [V-1 :0];
|
| 327 |
|
|
wire [V-1 : 0] mux_out[V-1 : 0];
|
| 328 |
|
|
|
| 329 |
54 |
alirezamon |
wire [V-1 : 0] dstport_fifo_not_empty;
|
| 330 |
|
|
|
| 331 |
|
|
logic [WEIGHTw-1 : 0] iport_weight_next;
|
| 332 |
|
|
|
| 333 |
48 |
alirezamon |
assign smart_hdr_en = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
|
| 334 |
|
|
assign reset_ivc = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
|
| 335 |
|
|
assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
|
| 336 |
|
|
assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
|
| 337 |
54 |
alirezamon |
assign rd_hdr_fwft_fifo = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
|
| 338 |
48 |
alirezamon |
assign wr_hdr_fwft_fifo = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
|
| 339 |
|
|
assign ivc_request = ivc_not_empty;
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
54 |
alirezamon |
wire [V-1 : 0] flit_is_tail2;
|
| 343 |
48 |
alirezamon |
|
| 344 |
54 |
alirezamon |
|
| 345 |
|
|
pronoc_register #(.W(V)) reg1(
|
| 346 |
48 |
alirezamon |
.in (ovc_is_assigned_next),
|
| 347 |
|
|
.reset (reset ),
|
| 348 |
|
|
.clk (clk ),
|
| 349 |
|
|
.out (ovc_is_assigned ));
|
| 350 |
|
|
|
| 351 |
54 |
alirezamon |
pronoc_register #(.W(VV)) reg2(
|
| 352 |
48 |
alirezamon |
.in (assigned_ovc_num_next),
|
| 353 |
|
|
.reset (reset ),
|
| 354 |
|
|
.clk (clk ),
|
| 355 |
|
|
.out (assigned_ovc_num ));
|
| 356 |
|
|
|
| 357 |
54 |
alirezamon |
pronoc_register #(.W(V)) reg3(
|
| 358 |
48 |
alirezamon |
.in (rd_hdr_fwft_fifo),
|
| 359 |
|
|
.reset (reset ),
|
| 360 |
|
|
.clk (clk ),
|
| 361 |
|
|
.out (rd_hdr_fwft_fifo_delay ));
|
| 362 |
|
|
|
| 363 |
54 |
alirezamon |
pronoc_register #(.W(V)) reg4(
|
| 364 |
48 |
alirezamon |
.in (wr_hdr_fwft_fifo),
|
| 365 |
|
|
.reset (reset ),
|
| 366 |
|
|
.clk (clk ),
|
| 367 |
|
|
.out (wr_hdr_fwft_fifo_delay ));
|
| 368 |
|
|
|
| 369 |
54 |
alirezamon |
pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
|
| 370 |
|
|
.in (iport_weight_next ),
|
| 371 |
|
|
.reset (reset ),
|
| 372 |
|
|
.clk (clk ),
|
| 373 |
|
|
.out (iport_weight ));
|
| 374 |
48 |
alirezamon |
|
| 375 |
54 |
alirezamon |
|
| 376 |
|
|
pronoc_register #(.W(V)) credit_reg (
|
| 377 |
|
|
.in (ivc_num_getting_sw_grant & ~ multiple_dest),
|
| 378 |
|
|
.reset (reset),
|
| 379 |
|
|
.clk (clk),
|
| 380 |
|
|
.out (credit_out));
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
|
| 385 |
|
|
always @ (*)begin
|
| 386 |
|
|
iport_weight_next = iport_weight;
|
| 387 |
|
|
if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
|
| 388 |
|
|
end
|
| 389 |
48 |
alirezamon |
|
| 390 |
|
|
|
| 391 |
|
|
//extract header flit info
|
| 392 |
|
|
extract_header_flit_info #(
|
| 393 |
56 |
alirezamon |
.NOC_ID(NOC_ID),
|
| 394 |
|
|
.DATA_w(0)
|
| 395 |
|
|
) header_extractor (
|
| 396 |
|
|
.flit_in(flit_in),
|
| 397 |
|
|
.flit_in_wr(flit_in_wr),
|
| 398 |
|
|
.class_o(class_in),
|
| 399 |
|
|
.destport_o(destport_in),
|
| 400 |
|
|
.dest_e_addr_o(dest_e_addr_in),
|
| 401 |
|
|
.src_e_addr_o(src_e_addr_in),
|
| 402 |
|
|
.vc_num_o(vc_num_in),
|
| 403 |
|
|
.hdr_flit_wr_o(hdr_flit_wr),
|
| 404 |
|
|
.hdr_flg_o(hdr_flg_in),
|
| 405 |
|
|
.tail_flg_o(tail_flg_in),
|
| 406 |
|
|
.weight_o(weight_in),
|
| 407 |
|
|
.be_o( ),
|
| 408 |
|
|
.data_o( )
|
| 409 |
|
|
);
|
| 410 |
48 |
alirezamon |
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
genvar i;
|
| 414 |
|
|
generate
|
| 415 |
|
|
/* verilator lint_off WIDTH */
|
| 416 |
54 |
alirezamon |
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
|
| 417 |
48 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
mesh_tori_endp_addr_decode #(
|
| 422 |
56 |
alirezamon |
.TOPOLOGY(TOPOLOGY),
|
| 423 |
48 |
alirezamon |
.T1(T1),
|
| 424 |
|
|
.T2(T2),
|
| 425 |
|
|
.T3(T3),
|
| 426 |
|
|
.EAw(EAw)
|
| 427 |
|
|
)
|
| 428 |
|
|
endp_addr_decode
|
| 429 |
|
|
(
|
| 430 |
|
|
.e_addr(dest_e_addr_in),
|
| 431 |
|
|
.ex( ),
|
| 432 |
|
|
.ey( ),
|
| 433 |
|
|
.el(endp_l_in),
|
| 434 |
|
|
.valid( )
|
| 435 |
|
|
);
|
| 436 |
|
|
end
|
| 437 |
|
|
/* verilator lint_off WIDTH */
|
| 438 |
54 |
alirezamon |
if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
|
| 439 |
48 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
fmesh_endp_addr_decode #(
|
| 444 |
|
|
.T1(T1),
|
| 445 |
|
|
.T2(T2),
|
| 446 |
|
|
.T3(T3),
|
| 447 |
|
|
.EAw(EAw)
|
| 448 |
|
|
)
|
| 449 |
|
|
endp_addr_decode
|
| 450 |
|
|
(
|
| 451 |
|
|
.e_addr(dest_e_addr_in),
|
| 452 |
|
|
.ex(),
|
| 453 |
|
|
.ey(),
|
| 454 |
|
|
.ep(endp_p_in),
|
| 455 |
|
|
.valid()
|
| 456 |
|
|
);
|
| 457 |
|
|
|
| 458 |
|
|
end
|
| 459 |
|
|
/* verilator lint_off WIDTH */
|
| 460 |
|
|
if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
|
| 461 |
|
|
/* verilator lint_on WIDTH */
|
| 462 |
|
|
|
| 463 |
|
|
fattree_destport_up_select #(
|
| 464 |
|
|
.K(T1),
|
| 465 |
|
|
.SW_LOC(SW_LOC)
|
| 466 |
|
|
)
|
| 467 |
|
|
static_sel
|
| 468 |
|
|
(
|
| 469 |
|
|
.destport_in(destport_in),
|
| 470 |
|
|
.destport_o(destport_in_encoded)
|
| 471 |
|
|
);
|
| 472 |
|
|
|
| 473 |
|
|
end else begin : other
|
| 474 |
|
|
assign destport_in_encoded = destport_in;
|
| 475 |
|
|
end
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
for (i=0;i
|
| 479 |
|
|
|
| 480 |
|
|
assign credit_init_val_out [i] = PORT_B [CRDTw-1 : 0 ];
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
|
| 484 |
|
|
.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]),
|
| 485 |
|
|
.bin_code(ivc_info[i].assigned_ovc_bin)
|
| 486 |
|
|
);
|
| 487 |
|
|
|
| 488 |
54 |
alirezamon |
assign ivc_info[i].single_flit_pck =
|
| 489 |
|
|
/* verilator lint_off WIDTH */
|
| 490 |
|
|
(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
|
| 491 |
|
|
/* verilator lint_on WIDTH */
|
| 492 |
|
|
(MIN_PCK_SIZE == 1)? flit_is_tail[i] & ~ovc_is_assigned[i] : 1'b0;
|
| 493 |
48 |
alirezamon |
assign ivc_info[i].ivc_req = ivc_request[i];
|
| 494 |
|
|
assign ivc_info[i].class_num = class_out[i];
|
| 495 |
|
|
assign ivc_info[i].flit_is_tail = flit_is_tail[i];
|
| 496 |
|
|
assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
|
| 497 |
|
|
assign ivc_info[i].candidate_ovc= candidate_ovcs [(i+1)*V-1 : i*V];
|
| 498 |
|
|
assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
|
| 499 |
|
|
assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
|
| 500 |
54 |
alirezamon |
assign ivc_info[i].dest_port_encoded=dest_port_encoded[i];
|
| 501 |
48 |
alirezamon |
//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
|
| 502 |
|
|
//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
|
| 503 |
|
|
if(P==MAX_P) begin :max_
|
| 504 |
|
|
assign ivc_info[i].destport_one_hot= destport_one_hot[i];
|
| 505 |
|
|
end else begin : no_max
|
| 506 |
|
|
assign ivc_info[i].destport_one_hot= {{(MAX_P-P){1'b0}},destport_one_hot[i]};
|
| 507 |
|
|
end
|
| 508 |
|
|
//synthesis translate_off
|
| 509 |
|
|
//check ivc info
|
| 510 |
|
|
//assigned ovc must be onehot coded
|
| 511 |
|
|
//assert property (@(posedge clk) $onehot0(ivc_info[i].assigned_ovc_num));
|
| 512 |
|
|
always @ (posedge clk )begin
|
| 513 |
|
|
if(~ $onehot0(ivc_info[i].assigned_ovc_num)) begin
|
| 514 |
|
|
$display ("ERROR: assigned OVC is not ont-hot coded %d,%m",ivc_info[i].assigned_ovc_num);
|
| 515 |
|
|
$finish;
|
| 516 |
|
|
end
|
| 517 |
|
|
end
|
| 518 |
|
|
//synthesis translate_on
|
| 519 |
|
|
|
| 520 |
54 |
alirezamon |
|
| 521 |
|
|
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
48 |
alirezamon |
class_ovc_table #(
|
| 525 |
|
|
.CVw(CVw),
|
| 526 |
|
|
.CLASS_SETTING(CLASS_SETTING),
|
| 527 |
|
|
.C(C),
|
| 528 |
|
|
.V(V)
|
| 529 |
|
|
)
|
| 530 |
|
|
class_table
|
| 531 |
|
|
(
|
| 532 |
|
|
.class_in(class_out[i]),
|
| 533 |
|
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
| 534 |
|
|
);
|
| 535 |
|
|
|
| 536 |
54 |
alirezamon |
if(PCK_TYPE == "MULTI_FLIT") begin : multi_flit
|
| 537 |
48 |
alirezamon |
|
| 538 |
|
|
always @ (*) begin
|
| 539 |
|
|
ovc_is_assigned_next[i] = ovc_is_assigned[i];
|
| 540 |
|
|
if( vsa_ctrl_in.ivc_reset[i] |
|
| 541 |
|
|
ssa_ctrl_in.ivc_reset[i] |
|
| 542 |
|
|
smart_ctrl_in.ivc_reset[i]
|
| 543 |
|
|
) ovc_is_assigned_next[i] = 1'b0;
|
| 544 |
|
|
|
| 545 |
|
|
else if( vsa_ctrl_in.ivc_num_getting_ovc_grant[i] |
|
| 546 |
|
|
(ssa_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ ssa_ctrl_in.ivc_single_flit_pck[i])|
|
| 547 |
|
|
(smart_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ smart_ctrl_in.ivc_single_flit_pck[i])
|
| 548 |
|
|
) ovc_is_assigned_next[i] = 1'b1;
|
| 549 |
|
|
end//always
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
always @(*) begin
|
| 553 |
|
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
| 554 |
|
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | smart_ctrl_in.ivc_num_getting_ovc_grant[i] ) begin
|
| 555 |
|
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
| 556 |
|
|
end
|
| 557 |
|
|
end
|
| 558 |
|
|
|
| 559 |
|
|
onehot_mux_1D #(
|
| 560 |
|
|
.N (3),
|
| 561 |
|
|
.W (V)
|
| 562 |
|
|
) hot_mux (
|
| 563 |
|
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
| 564 |
|
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
| 565 |
|
|
smart_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
| 566 |
|
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
| 567 |
|
|
.out (mux_out[i] )
|
| 568 |
|
|
);
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
54 |
alirezamon |
/*
|
| 572 |
48 |
alirezamon |
//tail fifo
|
| 573 |
|
|
fwft_fifo #(
|
| 574 |
|
|
.DATA_WIDTH(1),
|
| 575 |
|
|
.MAX_DEPTH (PORT_B),
|
| 576 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 577 |
|
|
)
|
| 578 |
|
|
tail_fifo
|
| 579 |
|
|
(
|
| 580 |
|
|
.din (tail_flg_in),
|
| 581 |
|
|
.wr_en (flit_wr[i]), // Write enable
|
| 582 |
|
|
.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word
|
| 583 |
|
|
.dout (flit_is_tail[i]), // Data out
|
| 584 |
|
|
.full ( ),
|
| 585 |
|
|
.nearly_full ( ),
|
| 586 |
|
|
.recieve_more_than_0 ( ),
|
| 587 |
|
|
.recieve_more_than_1 ( ),
|
| 588 |
|
|
.reset (reset),
|
| 589 |
|
|
.clk (clk)
|
| 590 |
|
|
);
|
| 591 |
54 |
alirezamon |
*/
|
| 592 |
|
|
|
| 593 |
|
|
end else begin :single_flit
|
| 594 |
|
|
//assign flit_is_tail[i]=1'b1;
|
| 595 |
48 |
alirezamon |
assign ovc_is_assigned_next[i] = 1'b0;
|
| 596 |
|
|
|
| 597 |
|
|
always @(*) begin
|
| 598 |
|
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
| 599 |
|
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin
|
| 600 |
|
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
| 601 |
|
|
end
|
| 602 |
|
|
end
|
| 603 |
|
|
|
| 604 |
|
|
onehot_mux_1D #(
|
| 605 |
|
|
.N (2),
|
| 606 |
|
|
.W (V)
|
| 607 |
|
|
) hot_mux (
|
| 608 |
|
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
| 609 |
|
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
| 610 |
|
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
| 611 |
|
|
.out (mux_out[i] )
|
| 612 |
|
|
);
|
| 613 |
|
|
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
end
|
| 617 |
|
|
//dest_e_addr_in fifo
|
| 618 |
|
|
if(SMART_EN) begin : smart_
|
| 619 |
|
|
|
| 620 |
|
|
fwft_fifo #(
|
| 621 |
|
|
.DATA_WIDTH(EAw),
|
| 622 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 623 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 624 |
|
|
)
|
| 625 |
|
|
dest_e_addr_fifo
|
| 626 |
|
|
(
|
| 627 |
|
|
.din (dest_e_addr_in),
|
| 628 |
|
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
| 629 |
|
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
| 630 |
|
|
.dout (ivc_info[i].dest_e_addr), // Data out
|
| 631 |
|
|
.full ( ),
|
| 632 |
|
|
.nearly_full ( ),
|
| 633 |
|
|
.recieve_more_than_0 ( ),
|
| 634 |
|
|
.recieve_more_than_1 ( ),
|
| 635 |
|
|
.reset (reset),
|
| 636 |
|
|
.clk (clk)
|
| 637 |
|
|
);
|
| 638 |
|
|
|
| 639 |
|
|
end else begin : no_smart
|
| 640 |
|
|
assign ivc_info[i].dest_e_addr = {EAw{1'bx}};
|
| 641 |
|
|
end
|
| 642 |
|
|
|
| 643 |
|
|
|
| 644 |
|
|
|
| 645 |
|
|
//class_fifo
|
| 646 |
|
|
if(C>1)begin :cb1
|
| 647 |
|
|
fwft_fifo #(
|
| 648 |
|
|
.DATA_WIDTH(Cw),
|
| 649 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 650 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 651 |
|
|
)
|
| 652 |
|
|
class_fifo
|
| 653 |
|
|
(
|
| 654 |
|
|
.din (class_in),
|
| 655 |
|
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
| 656 |
|
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
| 657 |
|
|
.dout (class_out[i]), // Data out
|
| 658 |
|
|
.full ( ),
|
| 659 |
|
|
.nearly_full ( ),
|
| 660 |
|
|
.recieve_more_than_0 ( ),
|
| 661 |
|
|
.recieve_more_than_1 ( ),
|
| 662 |
|
|
.reset (reset),
|
| 663 |
|
|
.clk (clk)
|
| 664 |
|
|
|
| 665 |
|
|
);
|
| 666 |
|
|
end else begin :c_num_1
|
| 667 |
|
|
assign class_out[i] = 1'b0;
|
| 668 |
|
|
end
|
| 669 |
|
|
|
| 670 |
54 |
alirezamon |
|
| 671 |
|
|
//localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
|
| 672 |
|
|
/* verilator lint_off WIDTH */
|
| 673 |
|
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
| 674 |
|
|
/* verilator lint_on WIDTH */
|
| 675 |
|
|
|
| 676 |
|
|
// for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions
|
| 677 |
|
|
|
| 678 |
|
|
fwft_fifo_with_output_clear #(
|
| 679 |
|
|
.DATA_WIDTH(DSTPw),
|
| 680 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 681 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 682 |
|
|
)
|
| 683 |
|
|
dest_fifo
|
| 684 |
|
|
(
|
| 685 |
|
|
.din(destport_in_encoded),
|
| 686 |
|
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
| 687 |
|
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
| 688 |
|
|
.dout(dest_port_multi[i]), // Data out
|
| 689 |
|
|
.full(),
|
| 690 |
|
|
.nearly_full(),
|
| 691 |
|
|
.recieve_more_than_0(),
|
| 692 |
|
|
.recieve_more_than_1(),
|
| 693 |
|
|
.reset(reset),
|
| 694 |
|
|
.clk(clk),
|
| 695 |
|
|
.clear(clear_dspt_mulicast [i]) // clear the destination port once it got the entire packet
|
| 696 |
|
|
);
|
| 697 |
|
|
|
| 698 |
|
|
//TODO remove multiple_dest[i] to see if it works?
|
| 699 |
|
|
|
| 700 |
|
|
assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};
|
| 701 |
|
|
|
| 702 |
|
|
// a fix priority arbiter.
|
| 703 |
56 |
alirezamon |
multicast_dst_sel #(
|
| 704 |
|
|
.NOC_ID(NOC_ID)
|
| 705 |
|
|
) sel_arb(
|
| 706 |
54 |
alirezamon |
.destport_in(dest_port_multi[i]),
|
| 707 |
|
|
.destport_out(dest_port_encoded[i])
|
| 708 |
|
|
);
|
| 709 |
|
|
|
| 710 |
|
|
//check if we have multiple port to send a packet to
|
| 711 |
|
|
is_onehot0 #(
|
| 712 |
|
|
.IN_WIDTH(DSTPw)
|
| 713 |
|
|
)
|
| 714 |
|
|
one_h
|
| 715 |
|
|
(
|
| 716 |
|
|
.in(dest_port_multi[i]),
|
| 717 |
|
|
.result(dst_onhot0[i])
|
| 718 |
|
|
);
|
| 719 |
|
|
assign multiple_dest[i]=~dst_onhot0[i];
|
| 720 |
|
|
|
| 721 |
|
|
|
| 722 |
|
|
end else begin : unicast
|
| 723 |
|
|
assign multiple_dest[i] = 1'b0;
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
48 |
alirezamon |
//lk_dst_fifo
|
| 727 |
|
|
fwft_fifo #(
|
| 728 |
|
|
.DATA_WIDTH(DSTPw),
|
| 729 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 730 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 731 |
|
|
)
|
| 732 |
|
|
lk_dest_fifo
|
| 733 |
|
|
(
|
| 734 |
|
|
.din (lk_destination_in_encoded),
|
| 735 |
|
|
.wr_en (wr_hdr_fwft_fifo_delay [i]), // Write enable
|
| 736 |
|
|
.rd_en (rd_hdr_fwft_fifo_delay [i]), // Read the next word
|
| 737 |
|
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
| 738 |
|
|
.full (),
|
| 739 |
|
|
.nearly_full (),
|
| 740 |
|
|
.recieve_more_than_0 (),
|
| 741 |
|
|
.recieve_more_than_1 (),
|
| 742 |
|
|
.reset (reset),
|
| 743 |
|
|
.clk (clk)
|
| 744 |
|
|
|
| 745 |
|
|
);
|
| 746 |
|
|
|
| 747 |
|
|
|
| 748 |
54 |
alirezamon |
|
| 749 |
|
|
/* verilator lint_off WIDTH */
|
| 750 |
|
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
| 751 |
|
|
/* verilator lint_on WIDTH */
|
| 752 |
|
|
//destport_fifo
|
| 753 |
|
|
fwft_fifo #(
|
| 754 |
|
|
.DATA_WIDTH(DSTPw),
|
| 755 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 756 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 757 |
|
|
)
|
| 758 |
|
|
dest_fifo
|
| 759 |
|
|
(
|
| 760 |
|
|
.din(destport_in_encoded),
|
| 761 |
|
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
| 762 |
|
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
| 763 |
|
|
.dout(dest_port_encoded[i]), // Data out
|
| 764 |
|
|
.full(),
|
| 765 |
|
|
.nearly_full(),
|
| 766 |
|
|
.recieve_more_than_0(),
|
| 767 |
|
|
.recieve_more_than_1(),
|
| 768 |
|
|
.reset(reset),
|
| 769 |
|
|
.clk(clk)
|
| 770 |
|
|
);
|
| 771 |
|
|
|
| 772 |
|
|
end else begin : adptv_dest
|
| 773 |
|
|
|
| 774 |
|
|
fwft_fifo_with_output_clear #(
|
| 775 |
|
|
.DATA_WIDTH(DSTPw),
|
| 776 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 777 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 778 |
|
|
)
|
| 779 |
|
|
dest_fifo
|
| 780 |
|
|
(
|
| 781 |
|
|
.din(destport_in_encoded),
|
| 782 |
|
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
| 783 |
|
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
| 784 |
|
|
.dout(dest_port_encoded[i]), // Data out
|
| 785 |
|
|
.full(),
|
| 786 |
|
|
.nearly_full(),
|
| 787 |
|
|
.recieve_more_than_0(),
|
| 788 |
|
|
.recieve_more_than_1(),
|
| 789 |
|
|
.reset(reset),
|
| 790 |
|
|
.clk(clk),
|
| 791 |
|
|
.clear(destport_clear[i]) // clear other destination ports once one of them is selected
|
| 792 |
|
|
);
|
| 793 |
|
|
|
| 794 |
|
|
|
| 795 |
|
|
end
|
| 796 |
|
|
end//unicast
|
| 797 |
48 |
alirezamon |
|
| 798 |
|
|
|
| 799 |
|
|
destp_generator #(
|
| 800 |
|
|
.TOPOLOGY(TOPOLOGY),
|
| 801 |
|
|
.ROUTE_NAME(ROUTE_NAME),
|
| 802 |
|
|
.ROUTE_TYPE(ROUTE_TYPE),
|
| 803 |
|
|
.T1(T1),
|
| 804 |
|
|
.NL(T3),
|
| 805 |
|
|
.P(P),
|
| 806 |
|
|
.DSTPw(DSTPw),
|
| 807 |
|
|
.PLw(PLw),
|
| 808 |
|
|
.PPSw(PPSw),
|
| 809 |
|
|
.SELF_LOOP_EN (SELF_LOOP_EN),
|
| 810 |
54 |
alirezamon |
.SW_LOC(SW_LOC),
|
| 811 |
|
|
.CAST_TYPE(CAST_TYPE)
|
| 812 |
48 |
alirezamon |
)
|
| 813 |
|
|
decoder
|
| 814 |
|
|
(
|
| 815 |
|
|
.destport_one_hot (destport_one_hot[i]),
|
| 816 |
54 |
alirezamon |
.dest_port_encoded(dest_port_encoded[i]),
|
| 817 |
48 |
alirezamon |
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
| 818 |
|
|
.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
|
| 819 |
|
|
.swap_port_presel(swap_port_presel[i]),
|
| 820 |
|
|
.port_pre_sel(port_pre_sel),
|
| 821 |
|
|
.odd_column(odd_column)
|
| 822 |
|
|
);
|
| 823 |
|
|
|
| 824 |
|
|
|
| 825 |
|
|
/* verilator lint_off WIDTH */
|
| 826 |
54 |
alirezamon |
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
|
| 827 |
48 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 828 |
|
|
// the router has multiple local ports. Save the destination local port
|
| 829 |
|
|
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
fwft_fifo #(
|
| 833 |
|
|
.DATA_WIDTH(ELw),
|
| 834 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 835 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 836 |
|
|
)
|
| 837 |
|
|
local_dest_fifo
|
| 838 |
|
|
(
|
| 839 |
|
|
.din(endp_l_in),
|
| 840 |
|
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
| 841 |
|
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
| 842 |
|
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
| 843 |
|
|
.full( ),
|
| 844 |
|
|
.nearly_full( ),
|
| 845 |
|
|
.recieve_more_than_0(),
|
| 846 |
|
|
.recieve_more_than_1(),
|
| 847 |
|
|
.reset(reset),
|
| 848 |
|
|
.clk(clk)
|
| 849 |
|
|
);
|
| 850 |
|
|
/* verilator lint_off WIDTH */
|
| 851 |
54 |
alirezamon |
end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
|
| 852 |
48 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 853 |
|
|
|
| 854 |
|
|
fwft_fifo #(
|
| 855 |
|
|
.DATA_WIDTH(Pw),
|
| 856 |
|
|
.MAX_DEPTH (MAX_PCK),
|
| 857 |
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| 858 |
|
|
)
|
| 859 |
|
|
local_dest_fifo
|
| 860 |
|
|
(
|
| 861 |
|
|
.din(endp_p_in),
|
| 862 |
|
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
| 863 |
|
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
| 864 |
|
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
| 865 |
|
|
.full( ),
|
| 866 |
|
|
.nearly_full( ),
|
| 867 |
|
|
.recieve_more_than_0(),
|
| 868 |
|
|
.recieve_more_than_1(),
|
| 869 |
|
|
.reset(reset),
|
| 870 |
|
|
.clk(clk)
|
| 871 |
|
|
);
|
| 872 |
|
|
|
| 873 |
|
|
end else begin : single_local
|
| 874 |
|
|
assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'bx}};
|
| 875 |
|
|
end
|
| 876 |
|
|
|
| 877 |
|
|
/* verilator lint_off WIDTH */
|
| 878 |
|
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
| 879 |
|
|
/* verilator lint_on WIDTH */
|
| 880 |
|
|
/*
|
| 881 |
|
|
weight_control #(
|
| 882 |
|
|
.WEIGHTw(WEIGHTw)
|
| 883 |
|
|
)
|
| 884 |
|
|
wctrl_per_vc
|
| 885 |
|
|
(
|
| 886 |
|
|
.sw_is_granted(ivc_num_getting_sw_grant[i]),
|
| 887 |
|
|
.flit_is_tail(flit_is_tail[i]),
|
| 888 |
|
|
.weight_is_consumed_o(vc_weight_is_consumed[i]),
|
| 889 |
|
|
.iport_weight(1), //(iport_weight),
|
| 890 |
|
|
.clk(clk),
|
| 891 |
|
|
.reset(reset)
|
| 892 |
|
|
);
|
| 893 |
|
|
*/
|
| 894 |
|
|
assign vc_weight_is_consumed[i] = 1'b1;
|
| 895 |
|
|
end else begin :no_wrra
|
| 896 |
|
|
assign vc_weight_is_consumed[i] = 1'bX;
|
| 897 |
|
|
end
|
| 898 |
|
|
|
| 899 |
|
|
end//for i
|
| 900 |
|
|
|
| 901 |
|
|
|
| 902 |
|
|
/* verilator lint_off WIDTH */
|
| 903 |
|
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
| 904 |
|
|
/* verilator lint_on WIDTH */
|
| 905 |
|
|
wire granted_flit_is_tail;
|
| 906 |
|
|
|
| 907 |
|
|
onehot_mux_1D #(
|
| 908 |
|
|
.W(1),
|
| 909 |
|
|
.N(V)
|
| 910 |
|
|
)onehot_mux(
|
| 911 |
|
|
.in(flit_is_tail),
|
| 912 |
|
|
.out(granted_flit_is_tail),
|
| 913 |
|
|
.sel(ivc_num_getting_sw_grant)
|
| 914 |
|
|
);
|
| 915 |
|
|
|
| 916 |
|
|
weight_control#(
|
| 917 |
|
|
.ARBITER_TYPE(SWA_ARBITER_TYPE),
|
| 918 |
|
|
.SW_LOC(SW_LOC),
|
| 919 |
|
|
.WEIGHTw(WEIGHTw),
|
| 920 |
|
|
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
|
| 921 |
|
|
.P(P),
|
| 922 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 923 |
|
|
)
|
| 924 |
|
|
wctrl_iport
|
| 925 |
|
|
(
|
| 926 |
|
|
.sw_is_granted(any_ivc_sw_request_granted),
|
| 927 |
|
|
.flit_is_tail(granted_flit_is_tail),
|
| 928 |
|
|
.weight_is_consumed_o(iport_weight_is_consumed),
|
| 929 |
|
|
.iport_weight(iport_weight),
|
| 930 |
|
|
.oports_weight(oports_weight),
|
| 931 |
|
|
.granted_dest_port(granted_dest_port),
|
| 932 |
|
|
.refresh_w_counter(refresh_w_counter),
|
| 933 |
|
|
.clk(clk),
|
| 934 |
|
|
.reset(reset)
|
| 935 |
|
|
);
|
| 936 |
|
|
|
| 937 |
|
|
end else begin :no_wrra
|
| 938 |
|
|
assign iport_weight_is_consumed=1'bX;
|
| 939 |
|
|
assign oports_weight = {WP{1'bX}};
|
| 940 |
|
|
end
|
| 941 |
|
|
|
| 942 |
|
|
/* verilator lint_off WIDTH */
|
| 943 |
|
|
if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
|
| 944 |
|
|
/* verilator lint_on WIDTH */
|
| 945 |
54 |
alirezamon |
|
| 946 |
|
|
|
| 947 |
|
|
|
| 948 |
|
|
|
| 949 |
|
|
/*
|
| 950 |
|
|
|
| 951 |
|
|
always @(posedge clk)
|
| 952 |
|
|
if ((ivc_not_empty & flit_is_tail2) != (ivc_not_empty & flit_is_tail))begin
|
| 953 |
|
|
$display("ERROR: %b !=%b",flit_is_tail2 , flit_is_tail ) ;
|
| 954 |
|
|
$finish;
|
| 955 |
|
|
end
|
| 956 |
|
|
*/
|
| 957 |
|
|
|
| 958 |
48 |
alirezamon |
|
| 959 |
|
|
flit_buffer #(
|
| 960 |
56 |
alirezamon |
.V(V),
|
| 961 |
48 |
alirezamon |
.B(PORT_B), // buffer space :flit per VC
|
| 962 |
56 |
alirezamon |
.SSA_EN(SSA_EN),
|
| 963 |
|
|
.Fw(Fw),
|
| 964 |
|
|
.PCK_TYPE(PCK_TYPE),
|
| 965 |
|
|
.CAST_TYPE(CAST_TYPE),
|
| 966 |
|
|
.DEBUG_EN(DEBUG_EN)
|
| 967 |
48 |
alirezamon |
)
|
| 968 |
|
|
the_flit_buffer
|
| 969 |
|
|
(
|
| 970 |
|
|
|
| 971 |
|
|
.din(flit_in), // Data in
|
| 972 |
|
|
.vc_num_wr(vc_num_in),//write virtual channel
|
| 973 |
|
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read virtual channel
|
| 974 |
|
|
.wr_en(flit_in_wr), // Write enable
|
| 975 |
|
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
| 976 |
|
|
.dout(buffer_out), // Data out
|
| 977 |
|
|
.vc_not_empty(ivc_not_empty),
|
| 978 |
|
|
.reset(reset),
|
| 979 |
|
|
.clk(clk),
|
| 980 |
54 |
alirezamon |
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
| 981 |
|
|
.multiple_dest( multiple_dest ),
|
| 982 |
|
|
.sub_rd_ptr_ld(reset_ivc) ,
|
| 983 |
|
|
.flit_is_tail(flit_is_tail)
|
| 984 |
48 |
alirezamon |
);
|
| 985 |
|
|
|
| 986 |
|
|
end else begin :spec//not nonspec comb
|
| 987 |
|
|
|
| 988 |
|
|
|
| 989 |
|
|
flit_buffer #(
|
| 990 |
56 |
alirezamon |
.V(V),
|
| 991 |
48 |
alirezamon |
.B(PORT_B), // buffer space :flit per VC
|
| 992 |
56 |
alirezamon |
.SSA_EN(SSA_EN),
|
| 993 |
|
|
.Fw(Fw),
|
| 994 |
|
|
.PCK_TYPE(PCK_TYPE),
|
| 995 |
|
|
.CAST_TYPE(CAST_TYPE),
|
| 996 |
|
|
.DEBUG_EN(DEBUG_EN)
|
| 997 |
48 |
alirezamon |
)
|
| 998 |
|
|
the_flit_buffer
|
| 999 |
|
|
(
|
| 1000 |
|
|
.din(flit_in), // Data in
|
| 1001 |
54 |
alirezamon |
.vc_num_wr(vc_num_in),//write virtual channel
|
| 1002 |
|
|
.vc_num_rd(ivc_num_getting_sw_grant),//read virtual channel
|
| 1003 |
48 |
alirezamon |
.wr_en(flit_in_wr), // Write enable
|
| 1004 |
|
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
| 1005 |
|
|
.dout(buffer_out), // Data out
|
| 1006 |
|
|
.vc_not_empty(ivc_not_empty),
|
| 1007 |
|
|
.reset(reset),
|
| 1008 |
|
|
.clk(clk),
|
| 1009 |
54 |
alirezamon |
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
| 1010 |
|
|
.multiple_dest( multiple_dest ),
|
| 1011 |
|
|
.sub_rd_ptr_ld(reset_ivc) ,
|
| 1012 |
|
|
.flit_is_tail(flit_is_tail)
|
| 1013 |
|
|
|
| 1014 |
48 |
alirezamon |
);
|
| 1015 |
|
|
|
| 1016 |
54 |
alirezamon |
end
|
| 1017 |
|
|
|
| 1018 |
|
|
|
| 1019 |
|
|
/* verilator lint_off WIDTH */
|
| 1020 |
|
|
if(CAST_TYPE== "UNICAST") begin : unicast
|
| 1021 |
|
|
/* verilator lint_on WIDTH */
|
| 1022 |
|
|
look_ahead_routing #(
|
| 1023 |
56 |
alirezamon |
.NOC_ID(NOC_ID),
|
| 1024 |
54 |
alirezamon |
.T1(T1),
|
| 1025 |
|
|
.T2(T2),
|
| 1026 |
|
|
.T3(T3),
|
| 1027 |
|
|
.T4(T4),
|
| 1028 |
|
|
.P(P),
|
| 1029 |
|
|
.RAw(RAw),
|
| 1030 |
|
|
.EAw(EAw),
|
| 1031 |
|
|
.DAw(DAw),
|
| 1032 |
|
|
.DSTPw(DSTPw),
|
| 1033 |
|
|
.SW_LOC(SW_LOC),
|
| 1034 |
|
|
.TOPOLOGY(TOPOLOGY),
|
| 1035 |
|
|
.ROUTE_NAME(ROUTE_NAME),
|
| 1036 |
|
|
.ROUTE_TYPE(ROUTE_TYPE)
|
| 1037 |
|
|
)
|
| 1038 |
|
|
lk_routing
|
| 1039 |
|
|
(
|
| 1040 |
|
|
.current_r_addr(current_r_addr),
|
| 1041 |
|
|
.neighbors_r_addr(neighbors_r_addr),
|
| 1042 |
|
|
.dest_e_addr(dest_e_addr_in),
|
| 1043 |
|
|
.src_e_addr(src_e_addr_in),
|
| 1044 |
|
|
.destport_encoded(destport_in_encoded),
|
| 1045 |
|
|
.lkdestport_encoded(lk_destination_in_encoded),
|
| 1046 |
|
|
.reset(reset),
|
| 1047 |
|
|
.clk(clk)
|
| 1048 |
|
|
);
|
| 1049 |
56 |
alirezamon |
end // unicast
|
| 1050 |
54 |
alirezamon |
|
| 1051 |
48 |
alirezamon |
endgenerate
|
| 1052 |
|
|
|
| 1053 |
54 |
alirezamon |
|
| 1054 |
48 |
alirezamon |
|
| 1055 |
|
|
header_flit_update_lk_route_ovc #(
|
| 1056 |
56 |
alirezamon |
.NOC_ID(NOC_ID),
|
| 1057 |
48 |
alirezamon |
.P(P)
|
| 1058 |
56 |
alirezamon |
) the_flit_update (
|
| 1059 |
48 |
alirezamon |
.flit_in (buffer_out),
|
| 1060 |
|
|
.flit_out (flit_out),
|
| 1061 |
|
|
.vc_num_in(ivc_num_getting_sw_grant),
|
| 1062 |
|
|
.lk_dest_all_in (lk_destination_encoded),
|
| 1063 |
|
|
.assigned_ovc_num (assigned_ovc_num),
|
| 1064 |
|
|
.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
|
| 1065 |
|
|
.lk_dest_not_registered(lk_destination_in_encoded),
|
| 1066 |
|
|
.sel (sel),
|
| 1067 |
|
|
.reset (reset),
|
| 1068 |
|
|
.clk (clk)
|
| 1069 |
|
|
);
|
| 1070 |
56 |
alirezamon |
|
| 1071 |
48 |
alirezamon |
|
| 1072 |
|
|
//synthesis translate_off
|
| 1073 |
|
|
//synopsys translate_off
|
| 1074 |
|
|
generate
|
| 1075 |
56 |
alirezamon |
if(DEBUG_EN) begin :debg
|
| 1076 |
48 |
alirezamon |
|
| 1077 |
|
|
always @ (posedge clk) begin
|
| 1078 |
|
|
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
|
| 1079 |
|
|
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
|
| 1080 |
|
|
$finish;
|
| 1081 |
|
|
end
|
| 1082 |
|
|
end//always
|
| 1083 |
|
|
|
| 1084 |
|
|
for (i=0;i
|
| 1085 |
|
|
always @ (posedge clk) begin
|
| 1086 |
|
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | (smart_ctrl_in.ivc_num_getting_ovc_grant[i] & (PCK_TYPE == "MULTI_FLIT")) )begin
|
| 1087 |
|
|
if( ~ $onehot (mux_out[i])) begin
|
| 1088 |
|
|
$display("%t: ERROR: granted OVC num is not onehot coded %b: %m",$time,mux_out[i]);
|
| 1089 |
|
|
$finish;
|
| 1090 |
|
|
end
|
| 1091 |
|
|
end
|
| 1092 |
|
|
if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin
|
| 1093 |
|
|
$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
|
| 1094 |
|
|
$finish;
|
| 1095 |
|
|
end
|
| 1096 |
|
|
end//always
|
| 1097 |
|
|
|
| 1098 |
54 |
alirezamon |
|
| 1099 |
|
|
|
| 1100 |
|
|
always @(posedge clk) begin
|
| 1101 |
|
|
if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}}) && (ivc_request[i]==1'b1)) begin
|
| 1102 |
|
|
$display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
|
| 1103 |
|
|
$finish;
|
| 1104 |
|
|
end
|
| 1105 |
|
|
end
|
| 1106 |
|
|
end//for
|
| 1107 |
|
|
|
| 1108 |
48 |
alirezamon |
/* verilator lint_off WIDTH */
|
| 1109 |
54 |
alirezamon |
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && CAST_TYPE== "UNICAST") begin : mesh_based
|
| 1110 |
48 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 1111 |
|
|
|
| 1112 |
|
|
debug_mesh_tori_route_ckeck #(
|
| 1113 |
|
|
.T1(T1),
|
| 1114 |
|
|
.T2(T2),
|
| 1115 |
|
|
.T3(T3),
|
| 1116 |
|
|
.ROUTE_TYPE(ROUTE_TYPE),
|
| 1117 |
|
|
.V(V),
|
| 1118 |
|
|
.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
|
| 1119 |
|
|
.SW_LOC(SW_LOC),
|
| 1120 |
|
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
| 1121 |
|
|
.TOPOLOGY(TOPOLOGY),
|
| 1122 |
|
|
.DSTPw(DSTPw),
|
| 1123 |
|
|
.RAw(RAw),
|
| 1124 |
|
|
.EAw(EAw)
|
| 1125 |
|
|
)
|
| 1126 |
|
|
route_ckeck
|
| 1127 |
|
|
(
|
| 1128 |
|
|
.reset(reset),
|
| 1129 |
|
|
.clk(clk),
|
| 1130 |
|
|
.hdr_flg_in(hdr_flg_in),
|
| 1131 |
|
|
.flit_in_wr(flit_in_wr),
|
| 1132 |
|
|
.vc_num_in(vc_num_in),
|
| 1133 |
|
|
.flit_is_tail(flit_is_tail),
|
| 1134 |
|
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
| 1135 |
|
|
.current_r_addr(current_r_addr),
|
| 1136 |
|
|
.dest_e_addr_in(dest_e_addr_in),
|
| 1137 |
|
|
.src_e_addr_in(src_e_addr_in),
|
| 1138 |
|
|
.destport_in(destport_in)
|
| 1139 |
|
|
);
|
| 1140 |
|
|
end//mesh
|
| 1141 |
|
|
end//DEBUG_EN
|
| 1142 |
|
|
endgenerate
|
| 1143 |
|
|
|
| 1144 |
|
|
`ifdef MONITORE_PATH
|
| 1145 |
|
|
genvar j;
|
| 1146 |
|
|
reg[V-1 :0] t1;
|
| 1147 |
|
|
generate
|
| 1148 |
|
|
for (j=0;j
|
| 1149 |
|
|
always @(posedge clk) begin
|
| 1150 |
56 |
alirezamon |
if(`pronoc_reset)begin
|
| 1151 |
48 |
alirezamon |
t1[j]<=1'b0;
|
| 1152 |
|
|
end else begin
|
| 1153 |
|
|
if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
|
| 1154 |
|
|
$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
|
| 1155 |
|
|
t1[j]<=1;
|
| 1156 |
|
|
end
|
| 1157 |
|
|
end
|
| 1158 |
|
|
end
|
| 1159 |
|
|
end
|
| 1160 |
|
|
endgenerate
|
| 1161 |
|
|
`endif
|
| 1162 |
|
|
// synopsys translate_on
|
| 1163 |
|
|
// synthesis translate_on
|
| 1164 |
|
|
|
| 1165 |
|
|
|
| 1166 |
|
|
|
| 1167 |
|
|
|
| 1168 |
|
|
endmodule
|
| 1169 |
|
|
|
| 1170 |
|
|
|
| 1171 |
|
|
|
| 1172 |
|
|
|
| 1173 |
|
|
|
| 1174 |
|
|
// decode and mask the destination port according to routing algorithm and topology
|
| 1175 |
|
|
module destp_generator #(
|
| 1176 |
|
|
parameter TOPOLOGY="MESH",
|
| 1177 |
|
|
parameter ROUTE_NAME="XY",
|
| 1178 |
|
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
| 1179 |
|
|
parameter T1=3,
|
| 1180 |
|
|
parameter NL=1,
|
| 1181 |
|
|
parameter P=5,
|
| 1182 |
|
|
parameter DSTPw=4,
|
| 1183 |
|
|
parameter PLw=1,
|
| 1184 |
|
|
parameter PPSw=4,
|
| 1185 |
|
|
parameter SW_LOC=0,
|
| 1186 |
54 |
alirezamon |
parameter SELF_LOOP_EN="NO",
|
| 1187 |
|
|
parameter CAST_TYPE = "UNICAST"
|
| 1188 |
48 |
alirezamon |
|
| 1189 |
|
|
)
|
| 1190 |
|
|
(
|
| 1191 |
|
|
destport_one_hot,
|
| 1192 |
|
|
dest_port_encoded,
|
| 1193 |
|
|
dest_port_out,
|
| 1194 |
|
|
endp_localp_num,
|
| 1195 |
|
|
swap_port_presel,
|
| 1196 |
|
|
port_pre_sel,
|
| 1197 |
|
|
odd_column
|
| 1198 |
|
|
);
|
| 1199 |
|
|
|
| 1200 |
|
|
localparam P_1= ( SELF_LOOP_EN=="NO")? P-1 : P;
|
| 1201 |
|
|
input [DSTPw-1 : 0] dest_port_encoded;
|
| 1202 |
|
|
input [PLw-1 : 0] endp_localp_num;
|
| 1203 |
|
|
output [P_1-1: 0] dest_port_out;
|
| 1204 |
|
|
output [P-1 : 0] destport_one_hot;
|
| 1205 |
|
|
input swap_port_presel;
|
| 1206 |
|
|
input [PPSw-1 : 0] port_pre_sel;
|
| 1207 |
|
|
input odd_column;
|
| 1208 |
|
|
|
| 1209 |
|
|
generate
|
| 1210 |
54 |
alirezamon |
|
| 1211 |
|
|
/* verilator lint_off WIDTH */
|
| 1212 |
|
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
| 1213 |
|
|
/* verilator lint_on WIDTH */
|
| 1214 |
|
|
// destination port is not coded for multicast/broadcast
|
| 1215 |
|
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
| 1216 |
|
|
remove_sw_loc_one_hot #(
|
| 1217 |
|
|
.P(P),
|
| 1218 |
|
|
.SW_LOC(SW_LOC)
|
| 1219 |
|
|
)
|
| 1220 |
|
|
remove_sw_loc
|
| 1221 |
|
|
(
|
| 1222 |
|
|
.destport_in(dest_port_encoded),
|
| 1223 |
|
|
.destport_out(dest_port_out)
|
| 1224 |
|
|
);
|
| 1225 |
|
|
end else begin : slp
|
| 1226 |
|
|
assign dest_port_out = dest_port_encoded;
|
| 1227 |
|
|
end
|
| 1228 |
|
|
/* verilator lint_off WIDTH */
|
| 1229 |
|
|
end else if(TOPOLOGY == "FATTREE" ) begin : fat
|
| 1230 |
|
|
/* verilator lint_on WIDTH */
|
| 1231 |
48 |
alirezamon |
fattree_destp_generator #(
|
| 1232 |
|
|
.K(T1),
|
| 1233 |
|
|
.P(P),
|
| 1234 |
|
|
.SW_LOC(SW_LOC),
|
| 1235 |
|
|
.DSTPw(DSTPw),
|
| 1236 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 1237 |
|
|
)
|
| 1238 |
|
|
destp_generator
|
| 1239 |
|
|
(
|
| 1240 |
|
|
.dest_port_in_encoded(dest_port_encoded),
|
| 1241 |
|
|
.dest_port_out(dest_port_out)
|
| 1242 |
|
|
);
|
| 1243 |
54 |
alirezamon |
/* verilator lint_off WIDTH */
|
| 1244 |
48 |
alirezamon |
end else if (TOPOLOGY == "TREE") begin :tree
|
| 1245 |
54 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 1246 |
48 |
alirezamon |
tree_destp_generator #(
|
| 1247 |
|
|
.K(T1),
|
| 1248 |
|
|
.P(P),
|
| 1249 |
|
|
.SW_LOC(SW_LOC),
|
| 1250 |
|
|
.DSTPw(DSTPw),
|
| 1251 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 1252 |
|
|
)
|
| 1253 |
|
|
destp_generator
|
| 1254 |
|
|
(
|
| 1255 |
|
|
.dest_port_in_encoded(dest_port_encoded),
|
| 1256 |
|
|
.dest_port_out(dest_port_out)
|
| 1257 |
|
|
);
|
| 1258 |
|
|
/* verilator lint_off WIDTH */
|
| 1259 |
|
|
end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
|
| 1260 |
|
|
/* verilator lint_on WIDTH */
|
| 1261 |
|
|
mesh_torus_destp_generator #(
|
| 1262 |
|
|
.TOPOLOGY(TOPOLOGY),
|
| 1263 |
|
|
.ROUTE_NAME(ROUTE_NAME),
|
| 1264 |
|
|
.ROUTE_TYPE(ROUTE_TYPE),
|
| 1265 |
|
|
.P(P),
|
| 1266 |
|
|
.DSTPw(DSTPw),
|
| 1267 |
|
|
.NL(NL),
|
| 1268 |
|
|
.PLw(PLw),
|
| 1269 |
|
|
.PPSw(PPSw),
|
| 1270 |
|
|
.SW_LOC(SW_LOC),
|
| 1271 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 1272 |
|
|
)
|
| 1273 |
|
|
destp_generator
|
| 1274 |
|
|
(
|
| 1275 |
|
|
.dest_port_coded(dest_port_encoded),
|
| 1276 |
|
|
.endp_localp_num(endp_localp_num),
|
| 1277 |
|
|
.dest_port_out(dest_port_out),
|
| 1278 |
|
|
.swap_port_presel(swap_port_presel),
|
| 1279 |
|
|
.port_pre_sel(port_pre_sel),
|
| 1280 |
|
|
.odd_column(odd_column)// only needed for odd even routing
|
| 1281 |
|
|
);
|
| 1282 |
54 |
alirezamon |
/* verilator lint_off WIDTH */
|
| 1283 |
48 |
alirezamon |
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
| 1284 |
54 |
alirezamon |
/* verilator lint_on WIDTH */
|
| 1285 |
48 |
alirezamon |
fmesh_destp_generator #(
|
| 1286 |
|
|
.ROUTE_NAME(ROUTE_NAME),
|
| 1287 |
|
|
.ROUTE_TYPE(ROUTE_TYPE),
|
| 1288 |
|
|
.P(P),
|
| 1289 |
|
|
.DSTPw(DSTPw),
|
| 1290 |
|
|
.NL(NL),
|
| 1291 |
|
|
.PLw(PLw),
|
| 1292 |
|
|
.PPSw(PPSw),
|
| 1293 |
|
|
.SW_LOC(SW_LOC),
|
| 1294 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 1295 |
|
|
)
|
| 1296 |
|
|
destp_generator
|
| 1297 |
|
|
(
|
| 1298 |
|
|
.dest_port_coded(dest_port_encoded),
|
| 1299 |
|
|
.endp_localp_num(endp_localp_num),
|
| 1300 |
|
|
.dest_port_out(dest_port_out),
|
| 1301 |
|
|
.swap_port_presel(swap_port_presel),
|
| 1302 |
|
|
.port_pre_sel(port_pre_sel),
|
| 1303 |
|
|
.odd_column(odd_column) // only needed for odd even routing
|
| 1304 |
|
|
);
|
| 1305 |
|
|
end else begin :custom
|
| 1306 |
|
|
|
| 1307 |
|
|
custom_topology_destp_decoder #(
|
| 1308 |
|
|
.ROUTE_TYPE(ROUTE_TYPE),
|
| 1309 |
|
|
.DSTPw(DSTPw),
|
| 1310 |
|
|
.P(P),
|
| 1311 |
|
|
.SW_LOC(SW_LOC),
|
| 1312 |
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
| 1313 |
|
|
)
|
| 1314 |
|
|
destp_generator
|
| 1315 |
|
|
(
|
| 1316 |
|
|
.dest_port_in_encoded(dest_port_encoded),
|
| 1317 |
|
|
.dest_port_out(dest_port_out)
|
| 1318 |
|
|
);
|
| 1319 |
|
|
end
|
| 1320 |
|
|
|
| 1321 |
|
|
if(SELF_LOOP_EN=="NO") begin : nslp
|
| 1322 |
|
|
add_sw_loc_one_hot #(
|
| 1323 |
|
|
.P(P),
|
| 1324 |
|
|
.SW_LOC(SW_LOC)
|
| 1325 |
|
|
)add
|
| 1326 |
|
|
(
|
| 1327 |
|
|
.destport_in(dest_port_out),
|
| 1328 |
|
|
.destport_out(destport_one_hot)
|
| 1329 |
|
|
);
|
| 1330 |
|
|
|
| 1331 |
|
|
end else begin : slp
|
| 1332 |
|
|
assign destport_one_hot = dest_port_out;
|
| 1333 |
|
|
end
|
| 1334 |
|
|
|
| 1335 |
|
|
endgenerate
|
| 1336 |
|
|
|
| 1337 |
|
|
|
| 1338 |
|
|
|
| 1339 |
|
|
|
| 1340 |
|
|
|
| 1341 |
|
|
|
| 1342 |
|
|
|
| 1343 |
|
|
|
| 1344 |
|
|
endmodule
|
| 1345 |
|
|
|
| 1346 |
|
|
/******************
|
| 1347 |
|
|
* custom_topology_destp_decoder
|
| 1348 |
|
|
* ***************/
|
| 1349 |
|
|
|
| 1350 |
|
|
|
| 1351 |
|
|
module custom_topology_destp_decoder #(
|
| 1352 |
|
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
| 1353 |
|
|
parameter DSTPw=4,
|
| 1354 |
|
|
parameter P=5,
|
| 1355 |
|
|
parameter SW_LOC=0,
|
| 1356 |
|
|
parameter SELF_LOOP_EN="NO"
|
| 1357 |
|
|
)(
|
| 1358 |
|
|
dest_port_in_encoded,
|
| 1359 |
|
|
dest_port_out
|
| 1360 |
|
|
);
|
| 1361 |
|
|
|
| 1362 |
|
|
localparam
|
| 1363 |
|
|
P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
|
| 1364 |
|
|
MAXW =2**DSTPw;
|
| 1365 |
|
|
|
| 1366 |
|
|
input [DSTPw-1 : 0] dest_port_in_encoded;
|
| 1367 |
|
|
output [P_1-1 : 0] dest_port_out;
|
| 1368 |
|
|
|
| 1369 |
|
|
|
| 1370 |
|
|
wire [MAXW-1 : 0] dest_port_one_hot;
|
| 1371 |
|
|
|
| 1372 |
|
|
bin_to_one_hot #(
|
| 1373 |
|
|
.BIN_WIDTH(DSTPw),
|
| 1374 |
|
|
.ONE_HOT_WIDTH(MAXW)
|
| 1375 |
|
|
)
|
| 1376 |
|
|
conv
|
| 1377 |
|
|
(
|
| 1378 |
|
|
.bin_code(dest_port_in_encoded),
|
| 1379 |
|
|
.one_hot_code(dest_port_one_hot)
|
| 1380 |
|
|
);
|
| 1381 |
|
|
generate
|
| 1382 |
|
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
| 1383 |
|
|
remove_sw_loc_one_hot #(
|
| 1384 |
|
|
.P(P),
|
| 1385 |
|
|
.SW_LOC(SW_LOC)
|
| 1386 |
|
|
)
|
| 1387 |
|
|
remove_sw_loc
|
| 1388 |
|
|
(
|
| 1389 |
|
|
.destport_in(dest_port_one_hot[P-1 : 0]),
|
| 1390 |
|
|
.destport_out(dest_port_out)
|
| 1391 |
|
|
);
|
| 1392 |
|
|
end else begin : slp
|
| 1393 |
|
|
assign dest_port_out = dest_port_one_hot;
|
| 1394 |
|
|
end
|
| 1395 |
|
|
endgenerate
|
| 1396 |
|
|
//synthesis translate_off
|
| 1397 |
|
|
//synopsys translate_off
|
| 1398 |
|
|
|
| 1399 |
|
|
initial begin
|
| 1400 |
|
|
if( ROUTE_TYPE != "DETERMINISTIC") begin
|
| 1401 |
|
|
$display("%t: ERROR: Custom topologies can only support deterministic routing in the current version of ProNoC",$time);
|
| 1402 |
|
|
$finish;
|
| 1403 |
|
|
end
|
| 1404 |
|
|
end
|
| 1405 |
|
|
|
| 1406 |
|
|
|
| 1407 |
|
|
//synopsys translate_on
|
| 1408 |
|
|
//synthesis translate_on
|
| 1409 |
|
|
|
| 1410 |
|
|
endmodule
|
