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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [noc_top.sv] - Blame information for rev 56

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`include "pronoc_def.v"
/**********************************************************************
**    File:  noc_top.sv
**
**    Copyright (C) 2014-2017  Alireza Monemi
**
**    This file is part of ProNoC
**
**    ProNoC ( stands for Prototype Network-on-chip)  is free software:
**    you can redistribute it and/or modify it under the terms of the GNU
**    Lesser General Public License as published by the Free Software Foundation,
**    either version 2 of the License, or (at your option) any later version.
**
**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**     Public License for more details.
**
**     You should have received a copy of the GNU Lesser General Public
**     License along with ProNoC. If not, see .
**
**
**    Description:
**    the NoC top module.
**
**************************************************************/
 
 
 
module  noc_top #(
        parameter NOC_ID=0
) (
        reset,
        clk,
        chan_in_all,
        chan_out_all,
        router_event
);
 
        `NOC_CONF
 
        input   clk,reset;
        //Endpoints ports
        input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
        output  smartflit_chanel_t chan_out_all [NE-1 : 0];
        //Events
        output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
 
 
 
 
        generate
        /* verilator lint_off WIDTH */
        if (TOPOLOGY ==    "MESH" || TOPOLOGY ==    "FMESH" || TOPOLOGY ==  "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
        /* verilator lint_on WIDTH */
                mesh_torus_noc_top #(
                        .NOC_ID(NOC_ID)
                ) noc_top (
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                );
 
    end else if (TOPOLOGY == "FATTREE") begin : fat_
 
        fattree_noc_top #(
                        .NOC_ID(NOC_ID)
                ) noc_top (
                .reset         (reset        ),
                .clk           (clk          ),
                .chan_in_all   (chan_in_all  ),
                .chan_out_all  (chan_out_all ),
                .router_event  (router_event )
        );
 
 
    end else if (TOPOLOGY == "TREE") begin : tree_
        tree_noc_top  #(
                        .NOC_ID(NOC_ID)
                ) noc_top (
                .reset         (reset        ),
                .clk           (clk          ),
                .chan_in_all   (chan_in_all  ),
                .chan_out_all  (chan_out_all ),
                .router_event  (router_event )
        );
    end else if (TOPOLOGY == "STAR") begin : star_
        star_noc_top  #(
                        .NOC_ID(NOC_ID)
                ) noc_top (
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
        );
 
    end else begin :custom_
 
        custom_noc_top #(
                        .NOC_ID(NOC_ID)
                ) noc_top (
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                );
 
    end
    endgenerate
endmodule
 
 
 
 
 
 
/**********************************
The noc top module that can be called in Verilog module.
 
***********************************/
 
module  noc_top_v  #(
        parameter NOC_ID=0
)(
    flit_out_all,
    flit_out_wr_all,
    credit_in_all,
    flit_in_all,
    flit_in_wr_all,
    credit_out_all,
    reset,
    clk
 );
 
        `NOC_CONF
 
        input   clk,reset;
        output [NEFw-1 : 0] flit_out_all;
    output [NE-1 : 0] flit_out_wr_all;
    input  [NEV-1 : 0] credit_in_all;
    input  [NEFw-1 : 0] flit_in_all;
    input  [NE-1 : 0] flit_in_wr_all;
    output [NEV-1 : 0] credit_out_all;
 
 
        //struct typed array ports which cannot be caled in verilog
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
        smartflit_chanel_t chan_out_all [NE-1 : 0];
 
        noc_top  #(
                .NOC_ID(NOC_ID)
        ) the_top(
                .reset(reset),
                .clk(clk),
                .chan_in_all(chan_in_all),
                .chan_out_all(chan_out_all),
                .router_event  (  )
        );
 
 
        genvar i;
        generate
        for (i=0; i
                assign chan_in_all[i].flit_chanel.flit    = flit_in_all [Fw*(i+1)-1 : Fw*i];
                assign chan_in_all[i].flit_chanel.credit  = credit_in_all [V*(i+1)-1 : V*i];
                assign chan_in_all[i].flit_chanel.flit_wr  = flit_in_wr_all[i];
 
                assign flit_out_all [Fw*(i+1)-1 : Fw*i] = chan_out_all[i].flit_chanel.flit;
                assign credit_out_all [V*(i+1)-1 : V*i] = chan_out_all[i].flit_chanel.credit;
                assign flit_out_wr_all[i] = chan_out_all[i].flit_chanel.flit_wr;
 
        end
        endgenerate
 
endmodule
 

Line No.	Rev	Author	Line
1	54	alirezamon	`include "pronoc_def.v"
2	48	alirezamon	`/**********************************************************************`
3			`** File: noc_top.sv`
4			`**`
5			`** Copyright (C) 2014-2017 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			`** License along with ProNoC. If not, see .`
21			`**`
22			`**`
23			`** Description:`
24			`** the NoC top module.`
25			`**`
26			`**************************************************************/`
27
28
29
30	56	alirezamon	`module noc_top #(`
31			`parameter NOC_ID=0`
32			`) (`
33	48	alirezamon	`reset,`
34			`clk,`
35			`chan_in_all,`
36	54	alirezamon	`chan_out_all,`
37			`router_event`
38	48	alirezamon	`);`
39
40	56	alirezamon	`NOC_CONF
41	48	alirezamon
42			`input clk,reset;`
43	54	alirezamon	`//Endpoints ports`
44	48	alirezamon	`input smartflit_chanel_t chan_in_all [NE-1 : 0];`
45			`output smartflit_chanel_t chan_out_all [NE-1 : 0];`
46	54	alirezamon	`//Events`
47			`output router_event_t router_event [NR-1 : 0][MAX_P-1 : 0];`
48	48	alirezamon
49
50
51
52			`generate`
53			`/* verilator lint_off WIDTH */`
54			`if (TOPOLOGY == "MESH" \|\| TOPOLOGY == "FMESH" \|\| TOPOLOGY == "TORUS" \|\| TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE") begin : tori_noc`
55			`/* verilator lint_on WIDTH */`
56	56	alirezamon	`mesh_torus_noc_top #(`
57			`.NOC_ID(NOC_ID)`
58			`) noc_top (`
59	48	alirezamon	`.reset (reset ),`
60			`.clk (clk ),`
61			`.chan_in_all (chan_in_all ),`
62	54	alirezamon	`.chan_out_all (chan_out_all ),`
63			`.router_event (router_event )`
64	56	alirezamon	`);`
65	48	alirezamon
66			`end else if (TOPOLOGY == "FATTREE") begin : fat_`
67
68	56	alirezamon	`fattree_noc_top #(`
69			`.NOC_ID(NOC_ID)`
70			`) noc_top (`
71			`.reset (reset ),`
72			`.clk (clk ),`
73			`.chan_in_all (chan_in_all ),`
74			`.chan_out_all (chan_out_all ),`
75			`.router_event (router_event )`
76	48	alirezamon	`);`
77
78
79			`end else if (TOPOLOGY == "TREE") begin : tree_`
80	56	alirezamon	`tree_noc_top #(`
81			`.NOC_ID(NOC_ID)`
82			`) noc_top (`
83	48	alirezamon	`.reset (reset ),`
84			`.clk (clk ),`
85			`.chan_in_all (chan_in_all ),`
86	54	alirezamon	`.chan_out_all (chan_out_all ),`
87			`.router_event (router_event )`
88	48	alirezamon	`);`
89			`end else if (TOPOLOGY == "STAR") begin : star_`
90	56	alirezamon	`star_noc_top #(`
91			`.NOC_ID(NOC_ID)`
92			`) noc_top (`
93	48	alirezamon	`.reset (reset ),`
94			`.clk (clk ),`
95			`.chan_in_all (chan_in_all ),`
96	54	alirezamon	`.chan_out_all (chan_out_all ),`
97			`.router_event (router_event )`
98	56	alirezamon	`);`
99	48	alirezamon
100			`end else begin :custom_`
101
102	56	alirezamon	`custom_noc_top #(`
103			`.NOC_ID(NOC_ID)`
104			`) noc_top (`
105	48	alirezamon	`.reset (reset ),`
106			`.clk (clk ),`
107			`.chan_in_all (chan_in_all ),`
108	54	alirezamon	`.chan_out_all (chan_out_all ),`
109			`.router_event (router_event )`
110	48	alirezamon	`);`
111
112			`end`
113			`endgenerate`
114			`endmodule`
115
116
117
118
119
120
121			`/**********************************`
122	54	alirezamon	`The noc top module that can be called in Verilog module.`
123	48	alirezamon
124			`***********************************/`
125
126	56	alirezamon	`module noc_top_v #(`
127			`parameter NOC_ID=0`
128			`)(`
129	48	alirezamon	`flit_out_all,`
130			`flit_out_wr_all,`
131			`credit_in_all,`
132			`flit_in_all,`
133			`flit_in_wr_all,`
134			`credit_out_all,`
135			`reset,`
136			`clk`
137			`);`
138
139	56	alirezamon	`NOC_CONF
140	48	alirezamon
141			`input clk,reset;`
142			`output [NEFw-1 : 0] flit_out_all;`
143			`output [NE-1 : 0] flit_out_wr_all;`
144			`input [NEV-1 : 0] credit_in_all;`
145			`input [NEFw-1 : 0] flit_in_all;`
146			`input [NE-1 : 0] flit_in_wr_all;`
147			`output [NEV-1 : 0] credit_out_all;`
148
149
150			`//struct typed array ports which cannot be caled in verilog`
151			`smartflit_chanel_t chan_in_all [NE-1 : 0];`
152			`smartflit_chanel_t chan_out_all [NE-1 : 0];`
153
154	56	alirezamon	`noc_top #(`
155			`.NOC_ID(NOC_ID)`
156			`) the_top(`
157	48	alirezamon	`.reset(reset),`
158			`.clk(clk),`
159			`.chan_in_all(chan_in_all),`
160	54	alirezamon	`.chan_out_all(chan_out_all),`
161			`.router_event ( )`
162	48	alirezamon	`);`
163
164	56	alirezamon
165	48	alirezamon	`genvar i;`
166			`generate`
167			`for (i=0; i`
168			`assign chan_in_all[i].flit_chanel.flit = flit_in_all [Fw(i+1)-1 : Fwi];`
169			`assign chan_in_all[i].flit_chanel.credit = credit_in_all [V(i+1)-1 : Vi];`
170			`assign chan_in_all[i].flit_chanel.flit_wr = flit_in_wr_all[i];`
171
172			`assign flit_out_all [Fw(i+1)-1 : Fwi] = chan_out_all[i].flit_chanel.flit;`
173			`assign credit_out_all [V(i+1)-1 : Vi] = chan_out_all[i].flit_chanel.credit;`
174			`assign flit_out_wr_all[i] = chan_out_all[i].flit_chanel.flit_wr;`
175
176			`end`
177			`endgenerate`
178
179			`endmodule`
180

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [noc_top.sv] - Blame information for rev 56