`timescale 1ns/1ps
/**********************************************************************
** File: output_ports.sv
**
** Copyright (C) 2014-2017 Alireza Monemi
**
** This file is part of ProNoC
**
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** you can redistribute it and/or modify it under the terms of the GNU
** Lesser General Public License as published by the Free Software Foundation,
** either version 2 of the License, or (at your option) any later version.
**
** ProNoC is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with ProNoC. If not, see .
**
**
** Description:
** output_ports module: contain output VC (OVC) status registers and credit counters,
**
**************************************************************/
module output_ports
import pronoc_pkg::*;
#(
parameter P = 5 // router port num
)(
vsa_ovc_allocated_all,
flit_is_tail_all,
assigned_ovc_num_all,
ovc_is_assigned_all,
dest_port_all,
nonspec_granted_dest_port_all,
credit_in_all,
nonspec_first_arbiter_granted_ivc_all,
ivc_num_getting_sw_grant,
ovc_avalable_all,
assigned_ovc_not_full_all,
port_pre_sel,
congestion_in_all,
granted_dst_is_from_a_single_flit_pck,
granted_ovc_num_all,
reset,
clk,
any_ovc_granted_in_outport_all,
vsa_credit_decreased_all,
vsa_ovc_released_all,
crossbar_flit_out_wr_all,
oport_info,
ovc_info,
vsa_ctrl_in,
ssa_ctrl_in,
smart_ctrl_in,
credit_init_val_in
);
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2j) begin: hh
assign ovc_released_gen [i][j] = ovc_released[j][i-V];
assign credit_decreased_gen[i][j] = credit_decreased[j][i-V];
end
end else begin :slp
assign ovc_released_gen [i][j] = ovc_released[j][i];
assign credit_decreased_gen[i][j] = credit_decreased [j][i];
end
end//j
assign vsa_ovc_released_all [i] = |ovc_released_gen[i];
assign vsa_credit_decreased_all [i] = (|credit_decreased_gen[i])|vsa_ovc_allocated_all[i];
end//i
if ( SELF_LOOP_EN=="NO") begin : nslp
//remove source port from the list
for(i=0;i< P;i=i+1) begin :port_loop
if(i==0) begin :i0
assign credit_in_perport [i]=credit_in_all [PV-1 : V];
assign full_perport [i]=full_all [PV-1 : V];
assign nearly_full_perport [i]=nearly_full_all [PV-1 : V];
end else if(i==(P-1)) begin :ip_1
assign credit_in_perport [i]=credit_in_all [PV-V-1 : 0];
assign full_perport [i]=full_all [PV-V-1 : 0];
assign nearly_full_perport [i]=nearly_full_all [PV-V-1 : 0];
end else begin : els
assign credit_in_perport [i]={credit_in_all [PV-1 : (i+1)*V],credit_in_all [(i*V)-1 : 0]};
assign full_perport [i]={full_all [PV-1 : (i+1)*V],full_all [(i*V)-1 : 0]};
assign nearly_full_perport [i]={nearly_full_all [PV-1 : (i+1)*V],nearly_full_all[(i*V)-1 : 0]};
end
end//for
end else begin: slp
for(i=0;i< P;i=i+1) begin :port_loop
assign credit_in_perport [i]=credit_in_all;
assign full_perport [i]=full_all;
assign nearly_full_perport [i]=nearly_full_all;
end
end
for(i=0; i0 && ovc_num[i] >0 && (ovc_num[i] & ovc_status)==0) $display ("%t :Error: OVC status%d missmatch:%b & %b, %m ",$time,i,ovc_num[i] , ovc_status);
end
end//for
endgenerate
endmodule
//synopsys translate_on
//synthesis translate_on
