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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [packet_injector.sv] - Blame information for rev 50

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`timescale  1ns/1ps
/****************************
 * This module can inject and eject packets from the NoC.
 * It can be used in simulation for injecting real application traces to the NoC
 * *************************/
 
 
module packet_injector
                import pronoc_pkg::*;
        (
                //general
                current_e_addr,
                reset,
                clk,
                //noc port
                chan_in,
                chan_out,
                //control interafce
                pck_injct_in,
                pck_injct_out
        );
 
        //general
        input reset,clk;
        input [EAw-1 :0 ] current_e_addr;
 
        // the destination endpoint address
        //NoC interface
        input   smartflit_chanel_t      chan_in;
        output  smartflit_chanel_t      chan_out;
        //control interafce
 
        input   pck_injct_t pck_injct_in;
        output  pck_injct_t pck_injct_out;
 
 
        wire  [RAw-1 :0 ] current_r_addr;
 
        wire  [DSTPw-1 : 0 ] destport;
        reg flit_wr;
 
 
 
 
 
 
        assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
 
 
 
 
        conventional_routing #(
                .TOPOLOGY(TOPOLOGY),
                .ROUTE_NAME(ROUTE_NAME),
                .ROUTE_TYPE(ROUTE_TYPE),
                .T1(T1),
                .T2(T2),
                .T3(T3),
                .RAw(RAw),
                .EAw(EAw),
                .DSTPw(DSTPw),
                .LOCATED_IN_NI(1)
        )
        routing_module
        (
                .reset(reset),
                .clk(clk),
                .current_r_addr(current_r_addr),
                .dest_e_addr(pck_injct_in.endp_addr),
                .src_e_addr(current_e_addr),
                .destport(destport)
        );
 
        localparam
                HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
                HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
                HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
 
        wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
        wire [Fw-1 : 0] hdr_flit_out;
 
        header_flit_generator #(
                .DATA_w(HDR_DATA_w)
        )
        the_header_flit_generator
        (
                .flit_out                       (hdr_flit_out),
                .vc_num_in                      (pck_injct_in.vc),
                .class_in                       (pck_injct_in.class_num),
                .dest_e_addr_in         (pck_injct_in.endp_addr),
                .src_e_addr_in          (current_e_addr),
                .weight_in                      (pck_injct_in.init_weight),
                .destport_in            (destport),
                .data_in                        (hdr_data_in),
                .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
        );
 
 
        localparam
                REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
                REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
                REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
                REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
                CNTw = log2(REMAIN_DAT_FLIT),
                MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
 
        reg [PCK_SIZw-1             :   0]  counter, counter_next;
        reg [CNTw-1                 :   0]  counter2,counter2_next;
        reg tail,head;
 
        wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
        wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
        enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
 
 
 
        wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
        wire [V-1 : 0]   vc_fifo_full;
 
 
        wire noc_ready;
 
        localparam
                LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
                LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
        genvar i;
        generate
                for(i=0; i
                        assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];
                end
                if(REMAIN_DAT_FLIT_F ) begin
 
                        assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
                end
        endgenerate
 
 
 
 
 
                one_hot_mux #(
                        .IN_WIDTH   (V ),
                        .SEL_WIDTH  (V ),
                        .OUT_WIDTH  (1 )
                        ) one_hot_mux1 (
                        .mux_in     (~ vc_fifo_full    ),
                        .mux_out    (noc_ready   ),
                        .sel        (pck_injct_in.vc       ));
 
 
 
 
                always @ (*) begin
                        counter_next = counter;
                        counter2_next =counter2;
                        flit_type_next =flit_type;
                        tail=1'b0;
                        head=1'b0;
                        flit_wr=0;
                        if(noc_ready)begin
                                case(flit_type)
                                        HEADER:begin
                                                if(pck_injct_in.pck_wr)begin
                                                        flit_wr=1;
                                                        counter_next = pck_injct_in.size-1;
                                                        counter2_next=0;
                                                        head=1'b1;
                                                        if(pck_injct_in.size == 1)begin
                                                                tail=1'b1;
                                                        end else if (pck_injct_in.size == 2) begin
                                                                flit_type_next = TAIL;
                                                        end else begin
                                                                flit_type_next = BODY;
                                                        end
                                                end
                                        end
                                        BODY: begin
                                                flit_wr=1;
                                                counter_next = counter -1'b1;
                                                counter2_next =counter2 +1'b1;
                                                if(counter == 2) begin
                                                        flit_type_next = TAIL;
                                                end
                                        end
                                        TAIL: begin
                                                flit_type_next = HEADER;
                                                flit_wr=1;
                                                tail=1'b1;
                                        end
                                endcase
 
                        end
                end
                reg [V-1 : 0] credit_o;
 
                always @ (posedge clk) begin
                        if(reset) begin
                                flit_type<=HEADER;
                                counter<=0;
                                counter2<=0;
                                credit_o<={V{1'b0}};
                        end else begin
                                flit_type<=flit_type_next;
                                counter<=counter_next;
                                counter2<=counter2_next;
                                if (chan_in.flit_chanel.flit_wr) credit_o<=  chan_in.flit_chanel.flit.vc;
                                else credit_o<={V{1'b0}};
                        end
                end
 
 
 
 
 
        injector_ovc_status #(
                .V(V),
                .B(LB),
                .CRDTw(CRDTw)
        )
        the_ovc_status
        (
                .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
                .wr_in(wr_vc_send),
                .credit_in(chan_in.flit_chanel.credit),
                .full_vc(vc_fifo_full),
                .nearly_full_vc( ),
                .empty_vc( ),
                .clk(clk),
                .reset(reset)
        );
 
 
 
 
 
 
 
        wire [HDR_DATA_w-1 : 0] hdr_data_o;
        hdr_flit_t hdr_flit_i;
 
        header_flit_info
        #(
                .DATA_w         (HDR_DATA_w       )
        ) extractor (
                .flit(chan_in.flit_chanel.flit),
                .hdr_flit(hdr_flit_i),
                .data_o(hdr_data_o)
        );
 
        wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
        reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
 
        genvar k;
 
        reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
        reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
        logic [15:0] h2t_counter [V-1 : 0];
        logic [15:0] h2t_counter_next [V-1 : 0];
 
 
 
        //synthesis translate_off
        wire [NEw-1 : 0] current_id;
        wire [NEw-1 : 0] sendor_id;
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr));
        //synthesis translate_on
 
 
        generate
                for(i=0; i
                        always@(*) begin
                                h2t_counter_next[i]=h2t_counter[i]+1'b1;
                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
                                                        h2t_counter_next[i]= 16'd0; // reset once header flit is received
                                end//hdr flit wr
                        end//always
 
 
 
 
                        always_ff @(posedge clk or posedge reset) begin
                                if (reset)  begin
                                        rsv_counter[i]<= {PCK_SIZw{1'b0}};
                                        h2t_counter[i]<= 16'd0;
                                        sender_endp_addr_reg [i]<= {EAw{1'b0}};
                                end else begin
                                        h2t_counter[i]<=h2t_counter_next[i];
                                        if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                if(chan_in.flit_chanel.flit.hdr_flag)begin
                                                        rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
                                                        sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
                                                        //synthesis translate_off
                                                        if(hdr_flit_i.dest_e_addr != current_e_addr) begin
                                                                $display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
                                                                $finish;
                                                        end//if hdr_flit_i
                                                        //synthesis translate_on
                                                end //if hdr_flag
                                                else rsv_counter[i]<= rsv_counter[i]+1'b1;
                                        end//flit wr
                                end//reset
                        end//always
 
 
 
 
                        for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
 
                                always_ff @(posedge clk or posedge reset) begin
                                        if (reset)  begin
                                                pck_data_o_gen [i][k] <= {Fpay{1'b0}};
 
                                        end else begin
                                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                        if (chan_in.flit_chanel.flit.hdr_flag )begin
                                                                if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
                                                        end
                                                        else begin
                                                                if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
 
                                                        end // else
                                                end //if
                                        end //else
                                end// always
 
                                        if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
                                        else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
                                        else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
 
                        end //for k
 
 
                        //synthesis translate_off
                        always @(posedge clk) begin
                                if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
                                        $display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
                                        $finish;
                                end
 
                        end
                        //synthesis translate_on
 
 
 
 
                end//for i
        endgenerate
 
        wire [V-1 : 0] vc_reg;
        wire tail_flag_reg, hdr_flag_reg;
 
 
        register #(.W(V))   register1 (.in(chan_in.flit_chanel.flit.vc),        .reset  (reset ), .clk (clk),.out(vc_reg));
        register #(.W(1))   register2 (.in(chan_in.flit_chanel.flit.hdr_flag),  .reset  (reset ), .clk (clk),.out(hdr_flag_reg));
        register #(.W(1))   register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset  (reset ), .clk (clk),.out(tail_flag_reg));
 
        wire [Vw-1 : 0] vc_bin;
 
        one_hot_to_bin #(
                .ONE_HOT_WIDTH  (V),
                .BIN_WIDTH      (Vw )
        ) one_hot_to_bin (
                .one_hot_code   (vc_reg  ),
                .bin_code       (vc_bin      )
        );
 
 
        assign pck_injct_out.data  =  pck_data_o[vc_bin];
        assign pck_injct_out.size  =  rsv_counter[vc_bin];
        assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
        assign pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};
        assign pck_injct_out.endp_addr =  sender_endp_addr_reg[vc_bin];
        assign pck_injct_out.vc = vc_reg;
        assign pck_injct_out.pck_wr = tail_flag_reg;
 
        assign chan_out.flit_chanel.flit.hdr_flag =head;
        assign chan_out.flit_chanel.flit.tail_flag=tail;
        assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
        assign chan_out.flit_chanel.flit_wr=flit_wr;
 
        assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
        assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
        assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
        assign chan_out.flit_chanel.credit= credit_o;
        assign chan_out.ctrl_chanel.credit_init_val= LB;
 
 
 
        distance_gen #(
                        .TOPOLOGY(TOPOLOGY),
                        .T1(T1),
                        .T2(T2),
                        .T3(T3),
                        .EAw(EAw),
                        .DISTw(DISTw)
                )
                the_distance_gen
                (
                        .src_e_addr(sender_endp_addr_reg[vc_bin]),
                        .dest_e_addr(current_e_addr),
                        .distance(pck_injct_out.distance)
                );
 
 
 
 
 
 
        //synthesis translate_off
        //`define MONITOR_RSV_DAT
 
 
 
        always @(posedge clk) begin
                if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
                        $display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
                        $finish;
                end
                if(pck_injct_in.pck_wr && (pck_injct_in.size
                        $display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
                        $finish;
                end
 
                `ifdef MONITOR_RSV_DAT
 
 
                if(pck_injct_in.pck_wr) begin
                        $display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
                                        pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
                end
 
                if(pck_injct_out.pck_wr) begin
                        $display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
                                        sendor_id,pck_injct_out.size,pck_injct_out.data);
                end
 
 
                `endif
 
        end
 
 
        //synthesis translate_on
 
 
 
 
 
endmodule
 
 
 
 
/******************
 *   ovc_status
 *******************/
 
module injector_ovc_status #(
                parameter V     =   4,
                parameter B =   16,
                parameter CRDTw =4
                )
                (
 
                input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
                input   [V-1            :0] wr_in,
                input   [V-1            :0] credit_in,
                output  [V-1            :0] full_vc,
                output  [V-1            :0] nearly_full_vc,
                output  [V-1            :0] empty_vc,
                input                       clk,
                input                       reset
                );
 
 
        function integer log2;
                input integer number; begin
                        log2=(number <=1) ? 1: 0;
                        while(2**log2
                                log2=log2+1;
                        end
                end
        endfunction // log2
 
 
        localparam  DEPTH_WIDTH =   log2(B+1);
 
 
        reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
        wire  [V-1 : 0] cand_vc_next;
 
 
        genvar i;
        generate
                for(i=0;i
                        `ifdef SYNC_RESET_MODE
                                always @ (posedge clk )begin
                                `else
                                        always @ (posedge clk or posedge reset)begin
                                        `endif
                                        if(reset)begin
                                                credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
                                        end else begin
                                                if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
                                                if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
                                        end //reset
                                end//always
 
                                assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
                                assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
                                assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
                        end//for
                        endgenerate
endmodule
 
 
 
 
/**************************************
 *
 *
 * ***********************************/
 
 
 
module packet_injector_verilator
import pronoc_pkg::*;
(
        //general
        current_e_addr,
        reset,
        clk,
        //noc port
        chan_in,
        chan_out,
        //control interafce
        pck_injct_in_data,
        pck_injct_in_size,
        pck_injct_in_endp_addr,
        pck_injct_in_class_num,
        pck_injct_in_init_weight,
        pck_injct_in_vc,
        pck_injct_in_pck_wr,
        pck_injct_in_ready,
 
        pck_injct_out_data,
        pck_injct_out_size,
        pck_injct_out_endp_addr,
        pck_injct_out_class_num,
        pck_injct_out_init_weight,
        pck_injct_out_vc,
        pck_injct_out_pck_wr,
        pck_injct_out_ready,
        pck_injct_out_distance,
        pck_injct_out_h2t_delay,
        min_pck_size
 
 
);
 
 
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
 
// the destination endpoint address
//NoC interface
input   smartflit_chanel_t      chan_in;
output  smartflit_chanel_t      chan_out;
//control interafce
 
 
 input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
 input [PCK_SIZw-1   : 0] pck_injct_in_size;
 input [EAw-1        : 0] pck_injct_in_endp_addr;
 input [Cw-1         : 0] pck_injct_in_class_num;
 input [WEIGHTw-1    : 0] pck_injct_in_init_weight;
 input [V-1          : 0] pck_injct_in_vc;
 input                    pck_injct_in_pck_wr;
 input [V-1          : 0] pck_injct_in_ready;
 
 output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
 output [PCK_SIZw-1   : 0] pck_injct_out_size;
 output [EAw-1        : 0] pck_injct_out_endp_addr;
 output [Cw-1         : 0] pck_injct_out_class_num;
 output [WEIGHTw-1    : 0] pck_injct_out_init_weight;
 output [V-1          : 0] pck_injct_out_vc;
 output                    pck_injct_out_pck_wr;
 output [V-1          : 0] pck_injct_out_ready;
 output [DISTw-1          : 0] pck_injct_out_distance;
 output [15                       : 0] pck_injct_out_h2t_delay;
 output [4                        : 0] min_pck_size;
 
 pck_injct_t pck_injct_in;
 pck_injct_t pck_injct_out;
 
 assign pck_injct_in.data         = pck_injct_in_data;
 assign pck_injct_in.size         = pck_injct_in_size;
 assign pck_injct_in.endp_addr    = pck_injct_in_endp_addr;
 assign pck_injct_in.class_num    = pck_injct_in_class_num;
 assign pck_injct_in.init_weight  = pck_injct_in_init_weight;
 assign pck_injct_in.vc           = pck_injct_in_vc;
 assign pck_injct_in.pck_wr       = pck_injct_in_pck_wr;
 assign pck_injct_in.ready        = pck_injct_in_ready;
 
 assign pck_injct_out_data        = pck_injct_out.data;
 assign pck_injct_out_size        = pck_injct_out.size;
 assign pck_injct_out_endp_addr   = pck_injct_out.endp_addr;
 assign pck_injct_out_class_num   = pck_injct_out.class_num;
 assign pck_injct_out_init_weight = pck_injct_out.init_weight;
 assign pck_injct_out_vc          = pck_injct_out.vc;
 assign pck_injct_out_pck_wr      = pck_injct_out.pck_wr;
 assign pck_injct_out_ready       = pck_injct_out.ready;
 assign pck_injct_out_distance    = pck_injct_out.distance;
 assign pck_injct_out_h2t_delay   = pck_injct_out.h2t_delay;
 
 packet_injector injector (
        .current_e_addr  (current_e_addr ),
        .reset           (reset          ),
        .clk             (clk            ),
        .chan_in         (chan_in        ),
        .chan_out        (chan_out       ),
        .pck_injct_in    (pck_injct_in   ),
        .pck_injct_out   (pck_injct_out  ));
 
 
 localparam
        HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
        HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
        HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,
        REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
        REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
        REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
        REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
        CNTw = log2(REMAIN_DAT_FLIT),
        MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
 assign  min_pck_size = MIN_PCK_SIZ[4:0];
 
 
// `ifdef VERILATOR
//      logic  endp_is_active   /*verilator public_flat_rd*/ ;
//
//      always @ (*) begin
//              endp_is_active  = 1'b0;
//              if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
//              if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
//              if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
//      end
// `endif
 
 
endmodule

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [packet_injector.sv] - Blame information for rev 50

Line No.	Rev	Author	Line
1	48	alirezamon	`timescale 1ns/1ps
2			`/****************************`
3			`* This module can inject and eject packets from the NoC.`
4			`* It can be used in simulation for injecting real application traces to the NoC`
5			`* *************************/`
6
7
8			`module packet_injector`
9			`import pronoc_pkg::*;`
10			`(`
11			`//general`
12			`current_e_addr,`
13			`reset,`
14			`clk,`
15			`//noc port`
16			`chan_in,`
17			`chan_out,`
18			`//control interafce`
19			`pck_injct_in,`
20			`pck_injct_out`
21			`);`
22
23			`//general`
24			`input reset,clk;`
25			`input [EAw-1 :0 ] current_e_addr;`
26
27			`// the destination endpoint address`
28			`//NoC interface`
29			`input smartflit_chanel_t chan_in;`
30			`output smartflit_chanel_t chan_out;`
31			`//control interafce`
32
33			`input pck_injct_t pck_injct_in;`
34			`output pck_injct_t pck_injct_out;`
35
36
37			`wire [RAw-1 :0 ] current_r_addr;`
38
39			`wire [DSTPw-1 : 0 ] destport;`
40			`reg flit_wr;`
41
42
43
44
45
46
47			`assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;`
48
49
50
51
52			`conventional_routing #(`
53			`.TOPOLOGY(TOPOLOGY),`
54			`.ROUTE_NAME(ROUTE_NAME),`
55			`.ROUTE_TYPE(ROUTE_TYPE),`
56			`.T1(T1),`
57			`.T2(T2),`
58			`.T3(T3),`
59			`.RAw(RAw),`
60			`.EAw(EAw),`
61			`.DSTPw(DSTPw),`
62			`.LOCATED_IN_NI(1)`
63			`)`
64			`routing_module`
65			`(`
66			`.reset(reset),`
67			`.clk(clk),`
68			`.current_r_addr(current_r_addr),`
69			`.dest_e_addr(pck_injct_in.endp_addr),`
70			`.src_e_addr(current_e_addr),`
71			`.destport(destport)`
72			`);`
73
74			`localparam`
75			`HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)`
76			`HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,`
77			`HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;`
78
79			`wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];`
80			`wire [Fw-1 : 0] hdr_flit_out;`
81
82			`header_flit_generator #(`
83			`.DATA_w(HDR_DATA_w)`
84			`)`
85			`the_header_flit_generator`
86			`(`
87			`.flit_out (hdr_flit_out),`
88			`.vc_num_in (pck_injct_in.vc),`
89			`.class_in (pck_injct_in.class_num),`
90			`.dest_e_addr_in (pck_injct_in.endp_addr),`
91			`.src_e_addr_in (current_e_addr),`
92			`.weight_in (pck_injct_in.init_weight),`
93			`.destport_in (destport),`
94			`.data_in (hdr_data_in),`
95			`.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data`
96			`);`
97
98
99			`localparam`
100			`REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,`
101			`REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),`
102			`REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,`
103			`REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,`
104			`CNTw = log2(REMAIN_DAT_FLIT),`
105			`MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;`
106
107
108			`reg [PCK_SIZw-1 : 0] counter, counter_next;`
109			`reg [CNTw-1 : 0] counter2,counter2_next;`
110			`reg tail,head;`
111
112			`wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];`
113			`wire [Fpay-1 : 0] dataIn = remain_dat[counter2];`
114			`enum {HEADER, BODY,TAIL} flit_type,flit_type_next;`
115
116
117
118			`wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};`
119			`wire [V-1 : 0] vc_fifo_full;`
120
121
122			`wire noc_ready;`
123
124			`localparam`
125			`LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,`
126			`LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;`
127			`genvar i;`
128			`generate`
129	50	alirezamon	`for(i=0; i`
130	48	alirezamon	`assign remain_dat [i] = pck_injct_in.data [Fpay(i+1)+HDR_DATA_w-1 : (Fpayi)+HDR_DATA_w];`
131			`end`
132			`if(REMAIN_DAT_FLIT_F ) begin`
133
134			`assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];`
135			`end`
136			`endgenerate`
137
138
139
140
141
142			`one_hot_mux #(`
143			`.IN_WIDTH (V ),`
144			`.SEL_WIDTH (V ),`
145			`.OUT_WIDTH (1 )`
146			`) one_hot_mux1 (`
147			`.mux_in (~ vc_fifo_full ),`
148			`.mux_out (noc_ready ),`
149			`.sel (pck_injct_in.vc ));`
150
151
152
153
154			`always @ (*) begin`
155			`counter_next = counter;`
156			`counter2_next =counter2;`
157			`flit_type_next =flit_type;`
158			`tail=1'b0;`
159			`head=1'b0;`
160			`flit_wr=0;`
161			`if(noc_ready)begin`
162			`case(flit_type)`
163			`HEADER:begin`
164			`if(pck_injct_in.pck_wr)begin`
165			`flit_wr=1;`
166			`counter_next = pck_injct_in.size-1;`
167			`counter2_next=0;`
168			`head=1'b1;`
169			`if(pck_injct_in.size == 1)begin`
170			`tail=1'b1;`
171			`end else if (pck_injct_in.size == 2) begin`
172			`flit_type_next = TAIL;`
173			`end else begin`
174			`flit_type_next = BODY;`
175			`end`
176			`end`
177			`end`
178			`BODY: begin`
179			`flit_wr=1;`
180			`counter_next = counter -1'b1;`
181			`counter2_next =counter2 +1'b1;`
182			`if(counter == 2) begin`
183			`flit_type_next = TAIL;`
184			`end`
185			`end`
186			`TAIL: begin`
187			`flit_type_next = HEADER;`
188			`flit_wr=1;`
189			`tail=1'b1;`
190			`end`
191			`endcase`
192
193			`end`
194			`end`
195			`reg [V-1 : 0] credit_o;`
196
197			`always @ (posedge clk) begin`
198			`if(reset) begin`
199			`flit_type<=HEADER;`
200			`counter<=0;`
201			`counter2<=0;`
202			`credit_o<={V{1'b0}};`
203			`end else begin`
204			`flit_type<=flit_type_next;`
205			`counter<=counter_next;`
206			`counter2<=counter2_next;`
207			`if (chan_in.flit_chanel.flit_wr) credit_o<= chan_in.flit_chanel.flit.vc;`
208			`else credit_o<={V{1'b0}};`
209			`end`
210			`end`
211
212
213
214
215
216			`injector_ovc_status #(`
217			`.V(V),`
218			`.B(LB),`
219			`.CRDTw(CRDTw)`
220			`)`
221			`the_ovc_status`
222			`(`
223			`.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),`
224			`.wr_in(wr_vc_send),`
225			`.credit_in(chan_in.flit_chanel.credit),`
226			`.full_vc(vc_fifo_full),`
227			`.nearly_full_vc( ),`
228			`.empty_vc( ),`
229			`.clk(clk),`
230			`.reset(reset)`
231			`);`
232
233
234
235
236
237
238
239			`wire [HDR_DATA_w-1 : 0] hdr_data_o;`
240			`hdr_flit_t hdr_flit_i;`
241
242			`header_flit_info`
243			`#(`
244			`.DATA_w (HDR_DATA_w )`
245			`) extractor (`
246			`.flit(chan_in.flit_chanel.flit),`
247			`.hdr_flit(hdr_flit_i),`
248			`.data_o(hdr_data_o)`
249			`);`
250
251			`wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];`
252			`reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];`
253
254			`genvar k;`
255
256			`reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];`
257			`reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];`
258			`logic [15:0] h2t_counter [V-1 : 0];`
259			`logic [15:0] h2t_counter_next [V-1 : 0];`
260
261
262
263			`//synthesis translate_off`
264			`wire [NEw-1 : 0] current_id;`
265			`wire [NEw-1 : 0] sendor_id;`
266			`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));`
267			`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr));`
268			`//synthesis translate_on`
269
270
271			`generate`
272			`for(i=0; i`
273			`always@(*) begin`
274			`h2t_counter_next[i]=h2t_counter[i]+1'b1;`
275			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin`
276			`h2t_counter_next[i]= 16'd0; // reset once header flit is received`
277			`end//hdr flit wr`
278			`end//always`
279
280
281
282
283			`always_ff @(posedge clk or posedge reset) begin`
284			`if (reset) begin`
285			`rsv_counter[i]<= {PCK_SIZw{1'b0}};`
286			`h2t_counter[i]<= 16'd0;`
287			`sender_endp_addr_reg [i]<= {EAw{1'b0}};`
288			`end else begin`
289			`h2t_counter[i]<=h2t_counter_next[i];`
290			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
291			`if(chan_in.flit_chanel.flit.hdr_flag)begin`
292			`rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};`
293			`sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;`
294			`//synthesis translate_off`
295			`if(hdr_flit_i.dest_e_addr != current_e_addr) begin`
296			`$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );`
297			`$finish;`
298			`end//if hdr_flit_i`
299			`//synthesis translate_on`
300			`end //if hdr_flag`
301			`else rsv_counter[i]<= rsv_counter[i]+1'b1;`
302			`end//flit wr`
303			`end//reset`
304			`end//always`
305
306
307
308
309			`for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_`
310
311			`always_ff @(posedge clk or posedge reset) begin`
312			`if (reset) begin`
313			`pck_data_o_gen [i][k] <= {Fpay{1'b0}};`
314
315			`end else begin`
316			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
317			`if (chan_in.flit_chanel.flit.hdr_flag )begin`
318			`if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;`
319			`end`
320			`else begin`
321			`if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;`
322
323			`end // else`
324			`end //if`
325			`end //else`
326			`end// always`
327
328			`if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];`
329			`else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];`
330			`else assign pck_data_o [i][(k)Fpay+HDR_DATA_w -1 : (k-1)Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];`
331
332			`end //for k`
333
334
335			`//synthesis translate_off`
336			`always @(posedge clk) begin`
337			`if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin`
338			`$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);`
339			`$finish;`
340			`end`
341
342			`end`
343			`//synthesis translate_on`
344
345
346
347
348			`end//for i`
349			`endgenerate`
350
351			`wire [V-1 : 0] vc_reg;`
352			`wire tail_flag_reg, hdr_flag_reg;`
353
354
355			`register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));`
356			`register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));`
357			`register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));`
358
359			`wire [Vw-1 : 0] vc_bin;`
360
361			`one_hot_to_bin #(`
362			`.ONE_HOT_WIDTH (V),`
363			`.BIN_WIDTH (Vw )`
364			`) one_hot_to_bin (`
365			`.one_hot_code (vc_reg ),`
366			`.bin_code (vc_bin )`
367			`);`
368
369
370			`assign pck_injct_out.data = pck_data_o[vc_bin];`
371			`assign pck_injct_out.size = rsv_counter[vc_bin];`
372			`assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];`
373			`assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};`
374			`assign pck_injct_out.endp_addr = sender_endp_addr_reg[vc_bin];`
375			`assign pck_injct_out.vc = vc_reg;`
376			`assign pck_injct_out.pck_wr = tail_flag_reg;`
377
378			`assign chan_out.flit_chanel.flit.hdr_flag =head;`
379			`assign chan_out.flit_chanel.flit.tail_flag=tail;`
380			`assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;`
381			`assign chan_out.flit_chanel.flit_wr=flit_wr;`
382
383			`assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;`
384			`assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};`
385			`assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};`
386			`assign chan_out.flit_chanel.credit= credit_o;`
387			`assign chan_out.ctrl_chanel.credit_init_val= LB;`
388
389
390
391			`distance_gen #(`
392			`.TOPOLOGY(TOPOLOGY),`
393			`.T1(T1),`
394			`.T2(T2),`
395			`.T3(T3),`
396			`.EAw(EAw),`
397			`.DISTw(DISTw)`
398			`)`
399			`the_distance_gen`
400			`(`
401			`.src_e_addr(sender_endp_addr_reg[vc_bin]),`
402			`.dest_e_addr(current_e_addr),`
403			`.distance(pck_injct_out.distance)`
404			`);`
405
406
407
408
409
410
411			`//synthesis translate_off`
412			//`define MONITOR_RSV_DAT
413
414
415
416			`always @(posedge clk) begin`
417			`if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin`
418			`$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);`
419			`$finish;`
420			`end`
421			`if(pck_injct_in.pck_wr && (pck_injct_in.size`
422			`$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );`
423			`$finish;`
424			`end`
425
426			`ifdef MONITOR_RSV_DAT
427
428
429			`if(pck_injct_in.pck_wr) begin`
430			`$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,`
431			`pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);`
432			`end`
433
434			`if(pck_injct_out.pck_wr) begin`
435			`$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,`
436			`sendor_id,pck_injct_out.size,pck_injct_out.data);`
437			`end`
438
439
440			`endif
441
442			`end`
443
444
445			`//synthesis translate_on`
446
447
448
449
450
451			`endmodule`
452
453
454
455
456			`/******************`
457			`* ovc_status`
458			`*******************/`
459
460			`module injector_ovc_status #(`
461			`parameter V = 4,`
462			`parameter B = 16,`
463			`parameter CRDTw =4`
464			`)`
465			`(`
466
467			`input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,`
468			`input [V-1 :0] wr_in,`
469			`input [V-1 :0] credit_in,`
470			`output [V-1 :0] full_vc,`
471			`output [V-1 :0] nearly_full_vc,`
472			`output [V-1 :0] empty_vc,`
473			`input clk,`
474			`input reset`
475			`);`
476
477
478			`function integer log2;`
479			`input integer number; begin`
480			`log2=(number <=1) ? 1: 0;`
481			`while(2**log2`
482			`log2=log2+1;`
483			`end`
484			`end`
485			`endfunction // log2`
486
487
488			`localparam DEPTH_WIDTH = log2(B+1);`
489
490
491			`reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];`
492			`wire [V-1 : 0] cand_vc_next;`
493
494
495			`genvar i;`
496			`generate`
497			`for(i=0;i`
498			`ifdef SYNC_RESET_MODE
499			`always @ (posedge clk )begin`
500			`else
501			`always @ (posedge clk or posedge reset)begin`
502			`endif
503			`if(reset)begin`
504			`credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];`
505			`end else begin`
506			`if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;`
507			`if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;`
508			`end //reset`
509			`end//always`
510
511			`assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});`
512			`assign nearly_full_vc[i]= (credit[i] == 1) \| full_vc[i];`
513			`assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);`
514			`end//for`
515			`endgenerate`
516			`endmodule`
517
518
519
520
521			`/**************************************`
522			`*`
523			`*`
524			`* ***********************************/`
525
526
527
528			`module packet_injector_verilator`
529			`import pronoc_pkg::*;`
530			`(`
531			`//general`
532			`current_e_addr,`
533			`reset,`
534			`clk,`
535			`//noc port`
536			`chan_in,`
537			`chan_out,`
538			`//control interafce`
539			`pck_injct_in_data,`
540			`pck_injct_in_size,`
541			`pck_injct_in_endp_addr,`
542			`pck_injct_in_class_num,`
543			`pck_injct_in_init_weight,`
544			`pck_injct_in_vc,`
545			`pck_injct_in_pck_wr,`
546			`pck_injct_in_ready,`
547
548			`pck_injct_out_data,`
549			`pck_injct_out_size,`
550			`pck_injct_out_endp_addr,`
551			`pck_injct_out_class_num,`
552			`pck_injct_out_init_weight,`
553			`pck_injct_out_vc,`
554			`pck_injct_out_pck_wr,`
555			`pck_injct_out_ready,`
556			`pck_injct_out_distance,`
557			`pck_injct_out_h2t_delay,`
558			`min_pck_size`
559
560
561			`);`
562
563
564			`//general`
565			`input reset,clk;`
566			`input [EAw-1 :0 ] current_e_addr;`
567
568			`// the destination endpoint address`
569			`//NoC interface`
570			`input smartflit_chanel_t chan_in;`
571			`output smartflit_chanel_t chan_out;`
572			`//control interafce`
573
574
575			`input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;`
576			`input [PCK_SIZw-1 : 0] pck_injct_in_size;`
577			`input [EAw-1 : 0] pck_injct_in_endp_addr;`
578			`input [Cw-1 : 0] pck_injct_in_class_num;`
579			`input [WEIGHTw-1 : 0] pck_injct_in_init_weight;`
580			`input [V-1 : 0] pck_injct_in_vc;`
581			`input pck_injct_in_pck_wr;`
582			`input [V-1 : 0] pck_injct_in_ready;`
583
584			`output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;`
585			`output [PCK_SIZw-1 : 0] pck_injct_out_size;`
586			`output [EAw-1 : 0] pck_injct_out_endp_addr;`
587			`output [Cw-1 : 0] pck_injct_out_class_num;`
588			`output [WEIGHTw-1 : 0] pck_injct_out_init_weight;`
589			`output [V-1 : 0] pck_injct_out_vc;`
590			`output pck_injct_out_pck_wr;`
591			`output [V-1 : 0] pck_injct_out_ready;`
592			`output [DISTw-1 : 0] pck_injct_out_distance;`
593			`output [15 : 0] pck_injct_out_h2t_delay;`
594			`output [4 : 0] min_pck_size;`
595
596			`pck_injct_t pck_injct_in;`
597			`pck_injct_t pck_injct_out;`
598
599			`assign pck_injct_in.data = pck_injct_in_data;`
600			`assign pck_injct_in.size = pck_injct_in_size;`
601			`assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;`
602			`assign pck_injct_in.class_num = pck_injct_in_class_num;`
603			`assign pck_injct_in.init_weight = pck_injct_in_init_weight;`
604			`assign pck_injct_in.vc = pck_injct_in_vc;`
605			`assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;`
606			`assign pck_injct_in.ready = pck_injct_in_ready;`
607
608			`assign pck_injct_out_data = pck_injct_out.data;`
609			`assign pck_injct_out_size = pck_injct_out.size;`
610			`assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;`
611			`assign pck_injct_out_class_num = pck_injct_out.class_num;`
612			`assign pck_injct_out_init_weight = pck_injct_out.init_weight;`
613			`assign pck_injct_out_vc = pck_injct_out.vc;`
614			`assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;`
615			`assign pck_injct_out_ready = pck_injct_out.ready;`
616			`assign pck_injct_out_distance = pck_injct_out.distance;`
617			`assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;`
618
619			`packet_injector injector (`
620			`.current_e_addr (current_e_addr ),`
621			`.reset (reset ),`
622			`.clk (clk ),`
623			`.chan_in (chan_in ),`
624			`.chan_out (chan_out ),`
625			`.pck_injct_in (pck_injct_in ),`
626			`.pck_injct_out (pck_injct_out ));`
627
628
629			`localparam`
630			`HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)`
631			`HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,`
632			`HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,`
633			`REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,`
634			`REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),`
635			`REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,`
636			`REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,`
637			`CNTw = log2(REMAIN_DAT_FLIT),`
638			`MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;`
639
640			`assign min_pck_size = MIN_PCK_SIZ[4:0];`
641
642
643			// `ifdef VERILATOR
644			`// logic endp_is_active /verilator public_flat_rd/ ;`
645			`//`
646			`// always @ (*) begin`
647			`// endp_is_active = 1'b0;`
648			`// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;`
649			`// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;`
650			`// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;`
651			`// end`
652			// `endif
653
654
655			`endmodule`