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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 56

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`include "pronoc_def.v"
 
 
/****************************************************************************
 * router_top.v
 ****************************************************************************/
 
/**
 * Module: router_top
 *
 *  add optional bypass links to two stage router.
 */
module router_top #(
        parameter NOC_ID=0,
        parameter P=5
)(
        current_r_id,
        current_r_addr,
 
        chan_in,
        chan_out,
 
        router_event,
 
        clk,
        reset
);
 
        `NOC_CONF
 
 
        localparam DISABLED =P;
 
        input [RAw-1 :  0]  current_r_addr;
        input [31 : 0] current_r_id;
 
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
 
        output router_event_t router_event [P-1 : 0];
 
 
 
        input   clk,reset;
 
        genvar i,j;
 
 
        //synthesis translate_off
        //synopsys  translate_off
        /* verilator lint_off WIDTH */
        initial begin
                if((SSA_EN=="YES")  &&(SMART_EN==1'b1))begin
                        $display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
                        $finish;
                end
                if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC")begin
                        $display("ERROR: SMART only works with non-speculative VSA");
                        $finish;
                end
                if((MIN_PCK_SIZE > 1) &&(PCK_TYPE == "SINGLE_FLIT")) begin
                        $display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
                        $finish;
                end
                if(((SSA_EN=="YES")  ||(SMART_EN==1'b1)) && CAST_TYPE!="UNICAST") begin
                        $display("ERROR: SMART or SAA do not support muticast/braodcast packets");
                        $finish;
                end
 
        end
        /* verilator lint_on WIDTH */
 
 
 
 
 
        logic report_active_ivcs = 0;
 
        generate
        for(i=0; i
                for(j=0; j
                        always @(posedge report_active_ivcs) begin
                                if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
                        end
                end
        end
        endgenerate
 
        //synopsys  translate_on
        //synthesis translate_on
 
 
 
        generate
        for(i=0; i
                assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
                assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
                assign router_event[i].pck_wr_i  = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
                assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
                assign router_event[i].pck_wr_o  = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
                assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
`ifdef ACTIVE_LOW_RESET_MODE
        assign router_event[i].active_high_reset = 1'b0;
 `else
        assign router_event[i].active_high_reset = 1'b1;
`endif
        end
        endgenerate
 
 
        flit_chanel_t r2_chan_in  [P-1 : 0];
        flit_chanel_t r2_chan_out [P-1 : 0];
 
        ivc_info_t       ivc_info    [P-1 : 0][V-1 : 0];
        ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
        iport_info_t iport_info  [P-1 : 0];
        oport_info_t oport_info  [P-1 : 0];
        smart_chanel_t smart_chanel_new  [P-1 : 0];
        smart_chanel_t smart_chanel_in   [P-1 : 0];
        smart_chanel_t smart_chanel_out  [P-1 : 0];
        smart_ctrl_t   smart_ctrl        [P-1 : 0];
 
 
        ctrl_chanel_t ctrl_in  [P-1 : 0];
        ctrl_chanel_t ctrl_out [P-1 : 0];
 
        generate
                for(i=0; i
                        assign  ctrl_in [i] = chan_in[i].ctrl_chanel;
                        assign  chan_out[i].ctrl_chanel= ctrl_out [i];
 
                end
        endgenerate
 
        // synthesis translate_off
 
        //header flit info, it is useful for debugin
        hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
        hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
 
        generate
                for(i=0; i
 
                        header_flit_info #(
                                .NOC_ID(NOC_ID)
                        ) in_extract(
                                .flit(chan_in[i].flit_chanel.flit),
                                .hdr_flit( hdr_flit_i[i]),
                                .data_o()
                        );
 
                        header_flit_info #(
                                .NOC_ID(NOC_ID)
                        ) out_extract(
                                .flit(chan_out[i].flit_chanel.flit),
                                .hdr_flit( hdr_flit_o[i]),
                                .data_o()
                        );
 
                        if(DEBUG_EN) begin :dbg
                                check_flit_chanel_type_is_in_order #(
                                        .V(V),
                                        .PCK_TYPE(PCK_TYPE),
                                        .MIN_PCK_SIZE(MIN_PCK_SIZE)
                                ) IVC_flit_type_check(
                                        .clk(clk),
                                        .reset(reset),
                                        .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
                                        .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
                                        .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
                                        .vc_num_in(chan_in[i].flit_chanel.flit.vc)
                                );
 
                                check_pck_size #(
                                        .NOC_ID(NOC_ID),
                                        .V(V),
                                        .MIN_PCK_SIZE(MIN_PCK_SIZE),
                                        .Fw(Fw),
                                        .DAw(DAw),
                                        .CAST_TYPE(CAST_TYPE),
                                        .NE(NE),
                                        .B(B),
                                        .LB(LB)
                                ) check_pck_siz(
                                        .clk(clk),
                                        .reset(reset),
                                        .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
                                        .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
                                        .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
                                        .vc_num_in(chan_in[i].flit_chanel.flit.vc),
                                        .dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
                                );
 
                        end
 
                end
        endgenerate
        // synthesis translate_on
 
 
 
 
 
        wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
        flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
 
        router_two_stage  #(//r2
                        .NOC_ID(NOC_ID),
                        .P(P)
                )router_ref(
                        .ivc_info(ivc_info),
                        .ovc_info(ovc_info),
                        .iport_info(iport_info),
                        .oport_info(oport_info),
                        .smart_ctrl_in(smart_ctrl),
                        .current_r_addr(current_r_addr),
                        .current_r_id(current_r_id),
                        .chan_in(r2_chan_in),
                        .chan_out(r2_chan_out),
                        .ctrl_in(ctrl_in),
                        .ctrl_out(ctrl_out),
                        .clk(clk),
                        .reset(reset)
                );
 
        generate
 
                if(SMART_EN) begin :smart
 
 
                        smart_forward_ivc_info  #(
                                .NOC_ID(NOC_ID),
                                .P(P)
                        ) forward_ivc(
                                .ivc_info(ivc_info),
                                .iport_info(iport_info),
                                .oport_info(oport_info),
                                .smart_chanel(smart_chanel_new),
                                .ovc_locally_requested(ovc_locally_requested),
                                .reset(reset),
                                .clk(clk)
                        );
 
                        smart_bypass_chanels #(
                                .NOC_ID(NOC_ID),
                                .P(P)
                        ) smart_bypass(
                                .ivc_info(ivc_info),
                                .iport_info(iport_info),
                                .oport_info(oport_info),
                                .smart_chanel_new(smart_chanel_new),
                                .smart_chanel_in(smart_chanel_in),
                                .smart_chanel_out(smart_chanel_out),
                                .smart_req(),
                                .reset(reset),
                                .clk(clk)
                        );
 
                        wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];
                        wire  [V-1  :  0]  credit_out [P-1 : 0];
                        wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
                        for(i=0;i
                                localparam SS_PORT = strieght_port(P,i);
                                if(SS_PORT == DISABLED) begin: smart_dis
                                        assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                        assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                        assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                                end
                                else begin :smart_en
                                        assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
                                        //smart allocator
                                        smart_allocator_per_iport #(
                                                .NOC_ID(NOC_ID),
                                                .P(P),
                                                .SW_LOC(i),
                                                .SS_PORT_LOC(SS_PORT)
                                        ) smart_allocator (
                                                .clk(clk),
                                                .reset(reset),
                                                .current_r_addr_i(current_r_addr),
                                                .neighbors_r_addr_i(neighbors_r_addr),
                                                .smart_chanel_i(chan_in[i].smart_chanel),
                                                .flit_chanel_i(chan_in[i].flit_chanel),
                                                .ivc_info (ivc_info[i]),
                                                .ss_ovc_info(ovc_info[SS_PORT]),
                                                .ovc_locally_requested(ovc_locally_requested[SS_PORT]),
                                                .ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
                                                .ss_port_link_reg_flit_wr(r2_chan_out[SS_PORT].flit_wr),
 
                                                .smart_ivc_single_flit_pck_o(smart_ctrl[i].ivc_single_flit_pck),
                                                .smart_destport_o(smart_ctrl[i].destport),
                                                .smart_lk_destport_o(smart_ctrl[i].lk_destport),
                                                .smart_hdr_flit_req_o(smart_ctrl[i].hdr_flit_req),
                                                .smart_ivc_smart_en_o(ivc_smart_en[i]),
                                                .smart_credit_o(smart_ctrl[i].credit_out),
                                                .smart_buff_space_decreased_o(smart_ctrl[SS_PORT].buff_space_decreased),
                                                .smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
                                                .smart_ivc_reset_o(smart_ctrl[i].ivc_reset),
                                                .smart_ivc_granted_ovc_num_o(smart_ctrl[i].ivc_granted_ovc_num),
                                                .smart_ovc_single_flit_pck_o(smart_ctrl[SS_PORT].ovc_single_flit_pck),
                                                .smart_ss_ovc_is_allocated_o(smart_ctrl[SS_PORT].ovc_is_allocated),
                                                .smart_ss_ovc_is_released_o     (smart_ctrl[SS_PORT].ovc_is_released),
                                                .smart_mask_available_ss_ovc_o(smart_ctrl[SS_PORT].mask_available_ovc)
 
                                        );
 
                                        assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
                                        assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
 
 
 
 
                                        // synthesis translate_off
                                        //assign chan_out[i].smart_chanel =(smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
                                        smart_chanel_check #(
                                                .NOC_ID(NOC_ID)
                                        ) check(
                                                .flit_chanel(chan_out[i].flit_chanel),
                                                .smart_chanel(chan_out[i].smart_chanel),
                                                .reset(reset),
                                                .clk(clk)
                                        );
                                        // synthesis translate_on
 
                                        assign smart_chanel_in[i] =   chan_in[i].smart_chanel;
 
 
                                        //r2 demux
                                        // flit_in_wr demux
                                        always @(*) begin
                                                chan_out[i].smart_chanel = smart_chanel_out[i];
                                                chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;
 
 
                                                //mask only flit_wr if smart_en is asserted
                                                r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                                //can replace destport here and remove lk rout from internal router
                                                if(smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
 
 
                                                //send flit_in to straight out port. Replace lk destport in header flit
                                                ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
                                                if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] =  smart_ctrl[i].lk_destport;
                                        end
 
                                        always @(*) begin
                                                // mux out flit channel
                                                chan_out[i].flit_chanel = r2_chan_out[i];
                                                chan_out[i].flit_chanel.credit    =  credit_out[i] ;
                                                if(smart_ctrl[SS_PORT].smart_en) begin
                                                        chan_out[i].flit_chanel.flit    =  ss_flit_chanel[i].flit;
                                                        chan_out[i].flit_chanel.flit_wr =  ss_flit_chanel[i].flit_wr;
 
                                                end
                                        end
 
                                        smart_credit_manage #(
                                                        .V(V),
                                                        .B(B)
                                                ) smart_credit_manage(
                                                        .credit_in(r2_chan_out[i].credit),
                                                        .smart_credit_in(smart_ctrl[i].credit_out),
                                                        .credit_out( credit_out[i]),
                                                        .reset(reset),
                                                        .clk(clk));
 
 
 
                                end //for
                        end//smart_en
 
 
 
                end else begin :no_smart
                        for(i=0;i
                                assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                        end//for
                end
        endgenerate
 
 
//`ifdef VERILATOR
//      logic  nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
//      logic  router_is_ideal /*verilator public_flat_rd*/ ;
//      logic  not_ideal_next,not_ideal;
//      integer ii,jj;
//      always @(*) begin
//              router_is_ideal = 1'b1;
//              not_ideal_next  = 1'b0;
//              for(ii=0; ii
//                      nb_router_active[ii]= 1'b0;
//                      if(chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
//                      if(chan_out[ii].flit_chanel.credit > {V{1'b0}}) nb_router_active[ii]=1'b1;
//                      if(chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}}) nb_router_active[ii]=1'b1;
//
//                      for(jj=0; jj
//                              //no active request is in any input queues
//                              if(ivc_info[ii][jj].ivc_req)begin
//                                      router_is_ideal=1'b0;
//                                      not_ideal_next=1'b1;
//                              end
//                      end
//                      //no output flit wr
//                      if(r2_chan_out[ii].flit_wr)  router_is_ideal=1'b0;
//              end
//              if(not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
//      end
//      pronoc_register #(      .W(1)) no_ideal_register(.in(not_ideal_next), .reset(reset),  .clk(clk), .out(not_ideal));
//`endif
 
 
 
endmodule
 
 
 
module router_top_v //to be used as top module in veralator
#(
        parameter NOC_ID=0,
        parameter P=5
)(
        current_r_addr,
        current_r_id,
 
        chan_in,
        chan_out,
 
        router_event,
 
        clk,
        reset
);
 
 
        `NOC_CONF
 
        input  [RAw-1 : 0] current_r_addr;
        input [31:0] current_r_id;
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
        input   reset,clk;
 
        output router_event_t router_event [P-1 : 0];
 
 
        router_top #(
                .NOC_ID(NOC_ID),
                .P(P)
        ) router (
                .current_r_id(current_r_id),
                .current_r_addr(current_r_addr),
                .chan_in(chan_in),
                .chan_out(chan_out),
                .router_event(router_event),
                .clk(clk),
                .reset(reset)
        );
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	54	alirezamon	`include "pronoc_def.v"
2	48	alirezamon
3
4			`/****************************************************************************`
5			`* router_top.v`
6			`****************************************************************************/`
7
8			`/**`
9			`* Module: router_top`
10			`*`
11			`* add optional bypass links to two stage router.`
12			`*/`
13	56	alirezamon	`module router_top #(`
14			`parameter NOC_ID=0,`
15			`parameter P=5`
16			`)(`
17			`current_r_id,`
18			`current_r_addr,`
19
20			`chan_in,`
21			`chan_out,`
22	48	alirezamon
23	56	alirezamon	`router_event,`
24	48	alirezamon
25	56	alirezamon	`clk,`
26			`reset`
27			`);`
28
29			`NOC_CONF
30	48	alirezamon
31
32			`localparam DISABLED =P;`
33
34			`input [RAw-1 : 0] current_r_addr;`
35	54	alirezamon	`input [31 : 0] current_r_id;`
36	48	alirezamon
37
38			`input smartflit_chanel_t chan_in [P-1 : 0];`
39			`output smartflit_chanel_t chan_out [P-1 : 0];`
40
41	54	alirezamon	`output router_event_t router_event [P-1 : 0];`
42
43
44
45	48	alirezamon	`input clk,reset;`
46
47			`genvar i,j;`
48
49
50			`//synthesis translate_off`
51			`//synopsys translate_off`
52			`/* verilator lint_off WIDTH */`
53			`initial begin`
54	56	alirezamon	`if((SSA_EN=="YES") &&(SMART_EN==1'b1))begin`
55	48	alirezamon	`$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");`
56			`$finish;`
57			`end`
58	56	alirezamon	`if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC")begin`
59	48	alirezamon	`$display("ERROR: SMART only works with non-speculative VSA");`
60			`$finish;`
61			`end`
62	56	alirezamon	`if((MIN_PCK_SIZE > 1) &&(PCK_TYPE == "SINGLE_FLIT")) begin`
63	48	alirezamon	`$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");`
64			`$finish;`
65			`end`
66	56	alirezamon	`if(((SSA_EN=="YES") \|\|(SMART_EN==1'b1)) && CAST_TYPE!="UNICAST") begin`
67	54	alirezamon	`$display("ERROR: SMART or SAA do not support muticast/braodcast packets");`
68			`$finish;`
69			`end`
70
71			`end`
72			`/* verilator lint_on WIDTH */`
73	48	alirezamon
74
75
76	54	alirezamon
77
78	48	alirezamon	`logic report_active_ivcs = 0;`
79
80			`generate`
81	56	alirezamon	`for(i=0; i`
82			`for(j=0; j`
83			`always @(posedge report_active_ivcs) begin`
84	54	alirezamon	`if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);`
85			`end`
86			`end`
87	48	alirezamon	`end`
88			`endgenerate`
89	54	alirezamon
90	48	alirezamon	`//synopsys translate_on`
91			`//synthesis translate_on`
92
93
94
95	54	alirezamon	`generate`
96	56	alirezamon	`for(i=0; i`
97	54	alirezamon	`assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;`
98			`assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;`
99			`assign router_event[i].pck_wr_i = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;`
100			`assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;`
101			`assign router_event[i].pck_wr_o = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;`
102			`assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;`
103	56	alirezamon	`ifdef ACTIVE_LOW_RESET_MODE
104			`assign router_event[i].active_high_reset = 1'b0;`
105			`else
106			`assign router_event[i].active_high_reset = 1'b1;`
107			`endif
108	54	alirezamon	`end`
109			`endgenerate`
110	48	alirezamon
111
112			`flit_chanel_t r2_chan_in [P-1 : 0];`
113			`flit_chanel_t r2_chan_out [P-1 : 0];`
114
115			`ivc_info_t ivc_info [P-1 : 0][V-1 : 0];`
116			`ovc_info_t ovc_info [P-1 : 0][V-1 : 0];`
117			`iport_info_t iport_info [P-1 : 0];`
118			`oport_info_t oport_info [P-1 : 0];`
119			`smart_chanel_t smart_chanel_new [P-1 : 0];`
120			`smart_chanel_t smart_chanel_in [P-1 : 0];`
121			`smart_chanel_t smart_chanel_out [P-1 : 0];`
122			`smart_ctrl_t smart_ctrl [P-1 : 0];`
123
124
125			`ctrl_chanel_t ctrl_in [P-1 : 0];`
126			`ctrl_chanel_t ctrl_out [P-1 : 0];`
127
128			`generate`
129	56	alirezamon	`for(i=0; i`
130	48	alirezamon	`assign ctrl_in [i] = chan_in[i].ctrl_chanel;`
131			`assign chan_out[i].ctrl_chanel= ctrl_out [i];`
132	54	alirezamon
133	48	alirezamon	`end`
134			`endgenerate`
135
136			`// synthesis translate_off`
137
138			`//header flit info, it is useful for debugin`
139			`hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info`
140			`hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info`
141
142			`generate`
143	56	alirezamon	`for(i=0; i`
144	48	alirezamon
145	56	alirezamon	`header_flit_info #(`
146			`.NOC_ID(NOC_ID)`
147			`) in_extract(`
148			`.flit(chan_in[i].flit_chanel.flit),`
149			`.hdr_flit( hdr_flit_i[i]),`
150			`.data_o()`
151			`);`
152	48	alirezamon
153	56	alirezamon	`header_flit_info #(`
154			`.NOC_ID(NOC_ID)`
155			`) out_extract(`
156			`.flit(chan_out[i].flit_chanel.flit),`
157			`.hdr_flit( hdr_flit_o[i]),`
158			`.data_o()`
159			`);`
160	48	alirezamon
161			`if(DEBUG_EN) begin :dbg`
162			`check_flit_chanel_type_is_in_order #(`
163			`.V(V),`
164			`.PCK_TYPE(PCK_TYPE),`
165			`.MIN_PCK_SIZE(MIN_PCK_SIZE)`
166	56	alirezamon	`) IVC_flit_type_check(`
167	48	alirezamon	`.clk(clk),`
168			`.reset(reset),`
169			`.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),`
170			`.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),`
171			`.flit_in_wr(chan_in[i].flit_chanel.flit_wr),`
172			`.vc_num_in(chan_in[i].flit_chanel.flit.vc)`
173			`);`
174	54	alirezamon
175			`check_pck_size #(`
176	56	alirezamon	`.NOC_ID(NOC_ID),`
177			`.V(V),`
178			`.MIN_PCK_SIZE(MIN_PCK_SIZE),`
179			`.Fw(Fw),`
180			`.DAw(DAw),`
181			`.CAST_TYPE(CAST_TYPE),`
182			`.NE(NE),`
183			`.B(B),`
184			`.LB(LB)`
185			`) check_pck_siz(`
186			`.clk(clk),`
187			`.reset(reset),`
188			`.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),`
189			`.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),`
190			`.flit_in_wr(chan_in[i].flit_chanel.flit_wr),`
191			`.vc_num_in(chan_in[i].flit_chanel.flit.vc),`
192			`.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])`
193			`);`
194	48	alirezamon
195	56	alirezamon	`end`
196	48	alirezamon
197			`end`
198			`endgenerate`
199			`// synthesis translate_on`
200
201
202
203
204
205			`wire [V-1 : 0] ovc_locally_requested [P-1 : 0];`
206			`flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port`
207
208			`router_two_stage #(//r2`
209	56	alirezamon	`.NOC_ID(NOC_ID),`
210			`.P(P)`
211			`)router_ref(`
212			`.ivc_info(ivc_info),`
213			`.ovc_info(ovc_info),`
214			`.iport_info(iport_info),`
215			`.oport_info(oport_info),`
216			`.smart_ctrl_in(smart_ctrl),`
217	48	alirezamon	`.current_r_addr(current_r_addr),`
218	54	alirezamon	`.current_r_id(current_r_id),`
219	56	alirezamon	`.chan_in(r2_chan_in),`
220			`.chan_out(r2_chan_out),`
221			`.ctrl_in(ctrl_in),`
222			`.ctrl_out(ctrl_out),`
223			`.clk(clk),`
224			`.reset(reset)`
225	48	alirezamon	`);`
226
227			`generate`
228
229			`if(SMART_EN) begin :smart`
230
231
232	56	alirezamon	`smart_forward_ivc_info #(`
233			`.NOC_ID(NOC_ID),`
234			`.P(P)`
235			`) forward_ivc(`
236			`.ivc_info(ivc_info),`
237			`.iport_info(iport_info),`
238			`.oport_info(oport_info),`
239			`.smart_chanel(smart_chanel_new),`
240			`.ovc_locally_requested(ovc_locally_requested),`
241			`.reset(reset),`
242			`.clk(clk)`
243			`);`
244	48	alirezamon
245	56	alirezamon	`smart_bypass_chanels #(`
246			`.NOC_ID(NOC_ID),`
247			`.P(P)`
248			`) smart_bypass(`
249			`.ivc_info(ivc_info),`
250			`.iport_info(iport_info),`
251			`.oport_info(oport_info),`
252			`.smart_chanel_new(smart_chanel_new),`
253			`.smart_chanel_in(smart_chanel_in),`
254			`.smart_chanel_out(smart_chanel_out),`
255			`.smart_req(),`
256			`.reset(reset),`
257			`.clk(clk)`
258			`);`
259	48	alirezamon
260			`wire [RAw-1: 0] neighbors_r_addr [P-1: 0];`
261			`wire [V-1 : 0] credit_out [P-1 : 0];`
262			`wire [V-1 : 0] ivc_smart_en [P-1 : 0];`
263	56	alirezamon	`for(i=0;i`
264			`localparam SS_PORT = strieght_port(P,i);`
265	48	alirezamon	`if(SS_PORT == DISABLED) begin: smart_dis`
266			`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
267			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
268			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
269			`end`
270			`else begin :smart_en`
271			`assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;`
272			`//smart allocator`
273			`smart_allocator_per_iport #(`
274	56	alirezamon	`.NOC_ID(NOC_ID),`
275			`.P(P),`
276			`.SW_LOC(i),`
277			`.SS_PORT_LOC(SS_PORT)`
278			`) smart_allocator (`
279			`.clk(clk),`
280			`.reset(reset),`
281			`.current_r_addr_i(current_r_addr),`
282			`.neighbors_r_addr_i(neighbors_r_addr),`
283			`.smart_chanel_i(chan_in[i].smart_chanel),`
284			`.flit_chanel_i(chan_in[i].flit_chanel),`
285			`.ivc_info (ivc_info[i]),`
286			`.ss_ovc_info(ovc_info[SS_PORT]),`
287			`.ovc_locally_requested(ovc_locally_requested[SS_PORT]),`
288			`.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),`
289			`.ss_port_link_reg_flit_wr(r2_chan_out[SS_PORT].flit_wr),`
290	48	alirezamon
291	56	alirezamon	`.smart_ivc_single_flit_pck_o(smart_ctrl[i].ivc_single_flit_pck),`
292			`.smart_destport_o(smart_ctrl[i].destport),`
293			`.smart_lk_destport_o(smart_ctrl[i].lk_destport),`
294			`.smart_hdr_flit_req_o(smart_ctrl[i].hdr_flit_req),`
295			`.smart_ivc_smart_en_o(ivc_smart_en[i]),`
296			`.smart_credit_o(smart_ctrl[i].credit_out),`
297			`.smart_buff_space_decreased_o(smart_ctrl[SS_PORT].buff_space_decreased),`
298			`.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),`
299			`.smart_ivc_reset_o(smart_ctrl[i].ivc_reset),`
300			`.smart_ivc_granted_ovc_num_o(smart_ctrl[i].ivc_granted_ovc_num),`
301			`.smart_ovc_single_flit_pck_o(smart_ctrl[SS_PORT].ovc_single_flit_pck),`
302			`.smart_ss_ovc_is_allocated_o(smart_ctrl[SS_PORT].ovc_is_allocated),`
303			`.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),`
304			`.smart_mask_available_ss_ovc_o(smart_ctrl[SS_PORT].mask_available_ovc)`
305	48	alirezamon
306	56	alirezamon	`);`
307	48	alirezamon
308			`assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];`
309			`assign smart_ctrl[i].smart_en = \|ivc_smart_en[i];`
310
311
312
313
314			`// synthesis translate_off`
315	56	alirezamon	`//assign chan_out[i].smart_chanel =(smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;`
316			`smart_chanel_check #(`
317			`.NOC_ID(NOC_ID)`
318			`) check(`
319			`.flit_chanel(chan_out[i].flit_chanel),`
320			`.smart_chanel(chan_out[i].smart_chanel),`
321			`.reset(reset),`
322			`.clk(clk)`
323			`);`
324	48	alirezamon	`// synthesis translate_on`
325
326			`assign smart_chanel_in[i] = chan_in[i].smart_chanel;`
327	54	alirezamon
328	48	alirezamon
329			`//r2 demux`
330			`// flit_in_wr demux`
331			`always @(*) begin`
332	54	alirezamon	`chan_out[i].smart_chanel = smart_chanel_out[i];`
333			`chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;`
334
335
336	48	alirezamon	`//mask only flit_wr if smart_en is asserted`
337			`r2_chan_in[i] = chan_in[i].flit_chanel;`
338			`//can replace destport here and remove lk rout from internal router`
339	56	alirezamon	`if(smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;`
340	54	alirezamon
341	48	alirezamon
342			`//send flit_in to straight out port. Replace lk destport in header flit`
343			`ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;`
344			`if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;`
345			`end`
346
347			`always @(*) begin`
348			`// mux out flit channel`
349			`chan_out[i].flit_chanel = r2_chan_out[i];`
350			`chan_out[i].flit_chanel.credit = credit_out[i] ;`
351			`if(smart_ctrl[SS_PORT].smart_en) begin`
352			`chan_out[i].flit_chanel.flit = ss_flit_chanel[i].flit;`
353			`chan_out[i].flit_chanel.flit_wr = ss_flit_chanel[i].flit_wr;`
354
355			`end`
356			`end`
357
358			`smart_credit_manage #(`
359	56	alirezamon	`.V(V),`
360			`.B(B)`
361			`) smart_credit_manage(`
362			`.credit_in(r2_chan_out[i].credit),`
363			`.smart_credit_in(smart_ctrl[i].credit_out),`
364			`.credit_out( credit_out[i]),`
365			`.reset(reset),`
366			`.clk(clk));`
367	48	alirezamon
368
369
370			`end //for`
371			`end//smart_en`
372
373
374
375			`end else begin :no_smart`
376	56	alirezamon	`for(i=0;i`
377	48	alirezamon	`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
378			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
379			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
380			`end//for`
381			`end`
382			`endgenerate`
383
384
385			//`ifdef VERILATOR
386			`// logic nb_router_active [P-1 : 0] /verilator public_flat_rd/ ;`
387			`// logic router_is_ideal /verilator public_flat_rd/ ;`
388			`// logic not_ideal_next,not_ideal;`
389			`// integer ii,jj;`
390	56	alirezamon	`// always @(*) begin`
391	48	alirezamon	`// router_is_ideal = 1'b1;`
392			`// not_ideal_next = 1'b0;`
393	56	alirezamon	`// for(ii=0; ii`
394	48	alirezamon	`// nb_router_active[ii]= 1'b0;`
395	56	alirezamon	`// if(chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;`
396			`// if(chan_out[ii].flit_chanel.credit > {V{1'b0}}) nb_router_active[ii]=1'b1;`
397			`// if(chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}}) nb_router_active[ii]=1'b1;`
398	48	alirezamon	`//`
399	56	alirezamon	`// for(jj=0; jj`
400	48	alirezamon	`// //no active request is in any input queues`
401			`// if(ivc_info[ii][jj].ivc_req)begin`
402			`// router_is_ideal=1'b0;`
403			`// not_ideal_next=1'b1;`
404			`// end`
405			`// end`
406			`// //no output flit wr`
407	56	alirezamon	`// if(r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;`
408	48	alirezamon	`// end`
409	56	alirezamon	`// if(not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one`
410	48	alirezamon	`// end`
411	56	alirezamon	`// pronoc_register #( .W(1)) no_ideal_register(.in(not_ideal_next), .reset(reset), .clk(clk), .out(not_ideal));`
412	48	alirezamon	//`endif
413
414
415
416			`endmodule`
417
418
419
420			`module router_top_v //to be used as top module in veralator`
421	56	alirezamon	`#(`
422			`parameter NOC_ID=0,`
423			`parameter P=5`
424			`)(`
425			`current_r_addr,`
426			`current_r_id,`
427	48	alirezamon
428	56	alirezamon	`chan_in,`
429			`chan_out,`
430	48	alirezamon
431	56	alirezamon	`router_event,`
432	54	alirezamon
433	56	alirezamon	`clk,`
434			`reset`
435			`);`
436	48	alirezamon
437	56	alirezamon
438			`NOC_CONF
439	48	alirezamon
440			`input [RAw-1 : 0] current_r_addr;`
441	54	alirezamon	`input [31:0] current_r_id;`
442	48	alirezamon
443			`input smartflit_chanel_t chan_in [P-1 : 0];`
444			`output smartflit_chanel_t chan_out [P-1 : 0];`
445	54	alirezamon	`input reset,clk;`
446
447			`output router_event_t router_event [P-1 : 0];`
448
449
450	56	alirezamon	`router_top #(`
451			`.NOC_ID(NOC_ID),`
452			`.P(P)`
453			`) router (`
454			`.current_r_id(current_r_id),`
455			`.current_r_addr(current_r_addr),`
456			`.chan_in(chan_in),`
457			`.chan_out(chan_out),`
458			`.router_event(router_event),`
459			`.clk(clk),`
460			`.reset(reset)`
461			`);`
462	48	alirezamon
463
464			`endmodule`
465
466

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 56