URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
// Quartus II SystemVerilog Template
//
// True Dual-Port RAM with different read/write addresses and single read/write clock
// and with a control for writing single bytes into the memory word; byte enable
// Read during write produces old data on ports A and B and old data on mixed ports
// For device families that do not support this mode (e.g. Stratix V) the ram is not inferred
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module byte_enabled_true_dual_port_ram #(
parameter INIT_FILE= "sw/ram/ram0.txt",// ram initial file in v format
parameter INITIAL_EN= "NO",
parameter int
BYTE_WIDTH = 8,
ADDRESS_WIDTH = 6,
BYTES = 4,
DATA_WIDTH_R = BYTE_WIDTH * BYTES
)
(
input [ADDRESS_WIDTH-1:0] addr1,
input [ADDRESS_WIDTH-1:0] addr2,
input [BYTES-1:0] be1,
input [BYTES-1:0] be2,
input [DATA_WIDTH_R-1:0] data_in1,
input [DATA_WIDTH_R-1:0] data_in2,
input we1, we2, clk,
output [DATA_WIDTH_R-1:0] data_out1,
output [DATA_WIDTH_R-1:0] data_out2
);
generate
if (BYTES==1) begin : byte_en1
byte_enabled_true_dual_port_ram_1
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==2) begin : byte_en2
byte_enabled_true_dual_port_ram_2
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==3) begin : byte_en3
byte_enabled_true_dual_port_ram_3
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==4) begin : byte_en4
byte_enabled_true_dual_port_ram_4
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==5) begin : byte_en5
byte_enabled_true_dual_port_ram_5
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==6) begin : byte_en6
byte_enabled_true_dual_port_ram_6
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==7) begin : byte_en7
byte_enabled_true_dual_port_ram_7
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==8) begin : byte_en8
byte_enabled_true_dual_port_ram_8
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==9) begin : byte_en9
byte_enabled_true_dual_port_ram_9
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==10) begin : byte_en10
byte_enabled_true_dual_port_ram_10
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==11) begin : byte_en11
byte_enabled_true_dual_port_ram_11
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==12) begin : byte_en12
byte_enabled_true_dual_port_ram_12
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==13) begin : byte_en13
byte_enabled_true_dual_port_ram_13
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==14) begin : byte_en14
byte_enabled_true_dual_port_ram_14
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
if (BYTES==15) begin : byte_en15
byte_enabled_true_dual_port_ram_15
#(
.BYTE_WIDTH(BYTE_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.INITIAL_EN(INITIAL_EN),
.INIT_FILE(INIT_FILE)
)
ram_inst
(
.addr1(addr1),
.addr2(addr2),
.be1(be1),
.be2(be2),
.data_in1(data_in1),
.data_in2(data_in2),
.we1(we1),
.we2(we2),
.clk(clk),
.data_out1(data_out1),
.data_out2(data_out2)
);
end
endgenerate
endmodule: byte_enabled_true_dual_port_ram
module byte_enabled_true_dual_port_ram_1 #(
parameter INIT_FILE= "sw/ram/ram0.txt",// ram initial file in v forma
parameter INITIAL_EN= "NO",
parameter int
BYTE_WIDTH = 8,
ADDRESS_WIDTH = 6,
BYTES = 1,
DATA_WIDTH_R = BYTE_WIDTH * BYTES
)
(
input [ADDRESS_WIDTH-1:0] addr1,
input [ADDRESS_WIDTH-1:0] addr2,
input [BYTES-1:0] be1,
input [BYTES-1:0] be2,
input [DATA_WIDTH_R-1:0] data_in1,
input [DATA_WIDTH_R-1:0] data_in2,
input we1, we2, clk,
output [DATA_WIDTH_R-1:0] data_out1,
output [DATA_WIDTH_R-1:0] data_out2
);
wire [BYTE_WIDTH-1 : 0] data_in_sep1[BYTES-1 : 0];
wire [BYTE_WIDTH-1 : 0] data_in_sep2[BYTES-1 : 0];
genvar i;
generate
for (i=0;i
