OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [script/] [run_modelsim] - Blame information for rev 56

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 45 alirezamon
#!/bin/bash
2 48 alirezamon
#/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin/vsim  -do model.tcl
3 43 alirezamon
#/home/alireza/altera/13.0sp1/modelsim_ase/bin/vsim  -do model.tcl
4 38 alirezamon
#/home/alireza/altera/modeltech/bin/vsim  -do model.tcl
5
 
6 48 alirezamon
SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
7
SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
8
 
9
#questasim
10 56 alirezamon
VSIM_BIN="${MODELSIM_BIN}/vsim"
11
export LM_LICENSE_FILE=${LM_LICENSE_FILE}
12 48 alirezamon
 
13
export LM_WORK_PLACE=${PRONOC_WORK}/simulation
14
export LM_FILE_LIST="$SCRPT_DIR_PATH/modelsim_filelist.f"
15
 
16
#"$SCRPT_DIR_PATH/../rtl/src_noc/noc_filelist.f $SCRPT_DIR_PATH/../rtl/src_modelsim/filelist.f"
17
 
18
 
19
echo "Start simulation" >&3
20
$VSIM_BIN  -quiet -64 -do model.tcl
21
wait
22
echo "End of Simulation" >&3

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.