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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_sim.v] - Blame information for rev 48

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1 16 alirezamon
/* $Id: aeMB2_sim.v,v 1.2 2007-12-29 00:31:48 sybreon Exp $
2
**
3
** AEMB2 SIMULATION WRAPPER
4
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
5
**
6
** This file is part of AEMB.
7
**
8
** AEMB is free software: you can redistribute it and/or modify it
9
** under the terms of the GNU Lesser General Public License as
10
** published by the Free Software Foundation, either version 3 of the
11
** License, or (at your option) any later version.
12
**
13
** AEMB is distributed in the hope that it will be useful, but WITHOUT
14
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
16
** Public License for more details.
17
**
18
** You should have received a copy of the GNU Lesser General Public
19
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
20
*/
21
`timescale  1ns/1ps
22
module aeMB2_sim (/*AUTOARG*/
23
   // Outputs
24
   iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
25
   dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
26
   cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
27
   // Inputs
28
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
29
   dwb_ack_i, cwb_dat_i, cwb_ack_i
30
   );
31
 
32
   parameter IWB=16;
33
   parameter DWB=16;
34
 
35
   parameter TXE = 1; ///< thread execution enable
36
 
37
   parameter MUL = 1; ///< enable hardware multiplier
38
   parameter BSF = 1; ///< enable barrel shifter
39
   parameter FSL = 1; ///< enable FSL bus
40
   parameter DIV = 0; ///< enable hardware divider   
41
 
42
   /*AUTOOUTPUT*/
43
   // Beginning of automatic outputs (from unused autoinst outputs)
44
   output [6:2]         cwb_adr_o;              // From sim of aeMB2_edk32.v
45
   output [31:0] cwb_dat_o;              // From sim of aeMB2_edk32.v
46
   output [3:0]          cwb_sel_o;              // From sim of aeMB2_edk32.v
47
   output               cwb_stb_o;              // From sim of aeMB2_edk32.v
48
   output [1:0]          cwb_tga_o;              // From sim of aeMB2_edk32.v
49
   output               cwb_wre_o;              // From sim of aeMB2_edk32.v
50
   output [DWB-1:2]     dwb_adr_o;              // From sim of aeMB2_edk32.v
51
   output               dwb_cyc_o;              // From sim of aeMB2_edk32.v
52
   output [31:0] dwb_dat_o;              // From sim of aeMB2_edk32.v
53
   output [3:0]          dwb_sel_o;              // From sim of aeMB2_edk32.v
54
   output               dwb_stb_o;              // From sim of aeMB2_edk32.v
55
   output               dwb_tga_o;              // From sim of aeMB2_edk32.v
56
   output               dwb_wre_o;              // From sim of aeMB2_edk32.v
57
   output [IWB-1:2]     iwb_adr_o;              // From sim of aeMB2_edk32.v
58
   output               iwb_stb_o;              // From sim of aeMB2_edk32.v
59
   output               iwb_tga_o;              // From sim of aeMB2_edk32.v
60
   output               iwb_wre_o;              // From sim of aeMB2_edk32.v
61
   // End of automatics
62
   /*AUTOINPUT*/
63
   // Beginning of automatic inputs (from unused autoinst inputs)
64
   input                cwb_ack_i;              // To sim of aeMB2_edk32.v
65
   input [31:0]          cwb_dat_i;              // To sim of aeMB2_edk32.v
66
   input                dwb_ack_i;              // To sim of aeMB2_edk32.v
67
   input [31:0]          dwb_dat_i;              // To sim of aeMB2_edk32.v
68
   input                iwb_ack_i;              // To sim of aeMB2_edk32.v
69
   input [31:0]          iwb_dat_i;              // To sim of aeMB2_edk32.v
70
   input                sys_clk_i;              // To sim of aeMB2_edk32.v
71
   input                sys_int_i;              // To sim of aeMB2_edk32.v
72
   input                sys_rst_i;              // To sim of aeMB2_edk32.v
73
   // End of automatics
74
   /*AUTOWIRE*/
75
 
76
   aeMB2_edk32
77
     #(/*AUTOINSTPARAM*/
78
       // Parameters
79
       .IWB                             (IWB),
80
       .DWB                             (DWB),
81
       .TXE                             (TXE),
82
       .MUL                             (MUL),
83
       .BSF                             (BSF),
84
       .FSL                             (FSL))
85
   sim
86
     (/*AUTOINST*/
87
      // Outputs
88
      .cwb_adr_o                        (cwb_adr_o[6:2]),
89
      .cwb_dat_o                        (cwb_dat_o[31:0]),
90
      .cwb_sel_o                        (cwb_sel_o[3:0]),
91
      .cwb_stb_o                        (cwb_stb_o),
92
      .cwb_tga_o                        (cwb_tga_o[1:0]),
93
      .cwb_wre_o                        (cwb_wre_o),
94
      .dwb_adr_o                        (dwb_adr_o[DWB-1:2]),
95
      .dwb_cyc_o                        (dwb_cyc_o),
96
      .dwb_dat_o                        (dwb_dat_o[31:0]),
97
      .dwb_sel_o                        (dwb_sel_o[3:0]),
98
      .dwb_stb_o                        (dwb_stb_o),
99
      .dwb_tga_o                        (dwb_tga_o),
100
      .dwb_wre_o                        (dwb_wre_o),
101
      .iwb_adr_o                        (iwb_adr_o[IWB-1:2]),
102
      .iwb_stb_o                        (iwb_stb_o),
103
      .iwb_tga_o                        (iwb_tga_o),
104
      .iwb_wre_o                        (iwb_wre_o),
105
      // Inputs
106
      .cwb_ack_i                        (cwb_ack_i),
107
      .cwb_dat_i                        (cwb_dat_i[31:0]),
108
      .dwb_ack_i                        (dwb_ack_i),
109
      .dwb_dat_i                        (dwb_dat_i[31:0]),
110
      .iwb_ack_i                        (iwb_ack_i),
111
      .iwb_dat_i                        (iwb_dat_i[31:0]),
112
      .sys_clk_i                        (sys_clk_i),
113
      .sys_int_i                        (sys_int_i),
114
      .sys_rst_i                        (sys_rst_i));
115
 
116
   // synopsys translate_off
117
 
118
   wire [31:0]           iwb_adr = {iwb_adr_o, 2'd0};
119
   wire [31:0]           dwb_adr = {dwb_adr_o, 2'd0};
120
   wire [31:0]           wMSR = sim.aslu.wMSR[31:0];
121
 
122
   always @(posedge sim.clk_i) if (sim.ena_i) begin
123
 
124
      $write ("\n", ($stime/10));
125 48 alirezamon
      $write (" T", sim.pha_i);
126
      $write(" PC=", iwb_adr);
127 16 alirezamon
 
128 48 alirezamon
      $write ("\t| ");
129 16 alirezamon
 
130
      case (sim.rOPC_IF)
131
        6'o00: if (sim.rRD_IF == 0) $write("   "); else $write("ADD");
132
        6'o01: $write("SUB");
133
        6'o02: $write("ADDC");
134
        6'o03: $write("SUBC");
135
        6'o04: $write("ADDK");
136
        6'o05: case (sim.rIMM_IF[1:0])
137
                 2'o0: $write("SUBK");
138
                 2'o1: $write("CMP");
139
                 2'o3: $write("CMPU");
140
                 default: $write("XXX");
141
               endcase // case (sim.rIMM_IF[1:0])
142
        6'o06: $write("ADDKC");
143
        6'o07: $write("SUBKC");
144
 
145
        6'o10: $write("ADDI");
146
        6'o11: $write("SUBI");
147
        6'o12: $write("ADDIC");
148
        6'o13: $write("SUBIC");
149
        6'o14: $write("ADDIK");
150
        6'o15: $write("SUBIK");
151
        6'o16: $write("ADDIKC");
152
        6'o17: $write("SUBIKC");
153
 
154
        6'o20: $write("MUL");
155
        6'o21: case (sim.rALT_IF[10:9])
156
                 2'o0: $write("BSRL");
157
                 2'o1: $write("BSRA");
158
                 2'o2: $write("BSLL");
159
                 default: $write("XXX");
160
               endcase // case (sim.rALT_IF[10:9])
161
        6'o22: $write("IDIV");
162
 
163
        6'o30: $write("MULI");
164
        6'o31: case (sim.rALT_IF[10:9])
165
                 2'o0: $write("BSRLI");
166
                 2'o1: $write("BSRAI");
167
                 2'o2: $write("BSLLI");
168
                 default: $write("XXX");
169
               endcase // case (sim.rALT_IF[10:9])
170
        6'o33: case (sim.rRB_IF[4:2])
171
                 3'o0: $write("GET");
172
                 3'o4: $write("PUT");
173
                 3'o2: $write("NGET");
174
                 3'o6: $write("NPUT");
175
                 3'o1: $write("CGET");
176
                 3'o5: $write("CPUT");
177
                 3'o3: $write("NCGET");
178
                 3'o7: $write("NCPUT");
179
               endcase // case (sim.rRB_IF[4:2])
180
 
181
        6'o40: $write("OR");
182
        6'o41: $write("AND");
183
        6'o42: if (sim.rRD_IF == 0) $write("   "); else $write("XOR");
184
        6'o43: $write("ANDN");
185
        6'o44: case (sim.rIMM_IF[6:5])
186
                 2'o0: $write("SRA");
187
                 2'o1: $write("SRC");
188
                 2'o2: $write("SRL");
189
                 2'o3: if (sim.rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
190
               endcase // case (sim.rIMM_IF[6:5])
191
 
192
        6'o45: $write("MOV");
193
        6'o46: case (sim.rRA_IF[3:2])
194
                 3'o0: $write("BR");
195
                 3'o1: $write("BRL");
196
                 3'o2: $write("BRA");
197
                 3'o3: $write("BRAL");
198
               endcase // case (sim.rRA_IF[3:2])
199
 
200
        6'o47: case (sim.rRD_IF[2:0])
201
                 3'o0: $write("BEQ");
202
                 3'o1: $write("BNE");
203
                 3'o2: $write("BLT");
204
                 3'o3: $write("BLE");
205
                 3'o4: $write("BGT");
206
                 3'o5: $write("BGE");
207
                 default: $write("XXX");
208
               endcase // case (sim.rRD_IF[2:0])
209
 
210
        6'o50: $write("ORI");
211
        6'o51: $write("ANDI");
212
        6'o52: $write("XORI");
213
        6'o53: $write("ANDNI");
214
        6'o54: $write("IMMI");
215
        6'o55: case (sim.rRD_IF[1:0])
216
                 2'o0: $write("RTSD");
217
                 2'o1: $write("RTID");
218
                 2'o2: $write("RTBD");
219
                 default: $write("XXX");
220
               endcase // case (sim.rRD_IF[1:0])
221
        6'o56: case (sim.rRA_IF[3:2])
222
                 3'o0: $write("BRI");
223
                 3'o1: $write("BRLI");
224
                 3'o2: $write("BRAI");
225
                 3'o3: $write("BRALI");
226
               endcase // case (sim.rRA_IF[3:2])
227
        6'o57: case (sim.rRD_IF[2:0])
228
                 3'o0: $write("BEQI");
229
                 3'o1: $write("BNEI");
230
                 3'o2: $write("BLTI");
231
                 3'o3: $write("BLEI");
232
                 3'o4: $write("BGTI");
233
                 3'o5: $write("BGEI");
234
                 default: $write("XXX");
235
               endcase // case (sim.rRD_IF[2:0])
236
 
237
        6'o60: $write("LBU");
238
        6'o61: $write("LHU");
239
        6'o62: $write("LW");
240
        6'o64: $write("SB");
241
        6'o65: $write("SH");
242
        6'o66: $write("SW");
243
 
244
        6'o70: $write("LBUI");
245
        6'o71: $write("LHUI");
246
        6'o72: $write("LWI");
247
        6'o74: $write("SBI");
248
        6'o75: $write("SHI");
249
        6'o76: $write("SWI");
250
 
251
        default: $write("XXX");
252
      endcase // case (sim.rOPC_IF)
253
 
254
      case (sim.rOPC_IF[3])
255 48 alirezamon
        1'b1: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
256
        1'b0: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF,"  ");
257 16 alirezamon
      endcase // case (sim.rOPC_IF[3])
258
 
259
      if (sim.bpcu.fHZD)
260
        $write ("*");
261
 
262
      // ALU
263
      $write("\t|");
264 48 alirezamon
      $write(" A=",sim.rOPA_OF);
265
      $write(" B=",sim.rOPB_OF);
266
      $write(" C=",sim.rOPX_OF);
267
      $write(" M=",sim.rOPM_OF);
268 16 alirezamon
 
269 48 alirezamon
      $write(" MSR=", wMSR," ");
270 16 alirezamon
 
271
      case (sim.rALU_OF)
272
        3'o0: $write(" ADD");
273
        3'o1: $write(" BSF");
274
        3'o2: $write(" SLM");
275
        3'o3: $write(" MOV");
276
        default: $write(" XXX");
277
      endcase // case (sim.rALU_OF)
278
 
279
      // MA
280
      $write ("\t| ");
281
      if (sim.dwb_stb_o)
282 48 alirezamon
        $write("@",sim.rRES_EX);
283 16 alirezamon
      else
284 48 alirezamon
        $write("=",sim.rRES_EX);
285 16 alirezamon
 
286
 
287
      case (sim.rBRA)
288
        2'b00: $write(" ");
289
        2'b01: $write(".");
290
        2'b10: $write("-");
291
        2'b11: $write("+");
292
      endcase // case (sim.rBRA)
293
 
294
      // WRITEBACK
295
      $write("\t|");
296
 
297
      if (|sim.rRD_MA) begin
298
         case (sim.rOPD_MA)
299
           2'o2: begin
300 48 alirezamon
              if (sim.rSEL_MA != 4'h0) $write("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
301
              if (sim.rSEL_MA == 4'h0) $write("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
302 16 alirezamon
           end
303 48 alirezamon
           2'o1: $write("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
304
           2'o0: $write("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
305 16 alirezamon
         endcase // case (sim.rOPD_MA)
306
      end
307
 
308
      /*
309
      // STORE
310
      if (dwb_stb_o & dwb_wre_o) begin
311 48 alirezamon
         $write("RAM(", dwb_adr ,")=", dwb_dat_o);
312 16 alirezamon
         case (dwb_sel_o)
313
           4'hF: $write(":L");
314
           4'h3,4'hC: $write(":W");
315
           4'h1,4'h2,4'h4,4'h8: $write(":B");
316
         endcase // case (dwb_sel_o)
317
 
318
      end
319
       */
320
   end // if (sim.ena_i)
321
 
322
   // synopsys translate_on
323
 
324
endmodule // aeMB2_sim
325
 
326
/* $Log: not supported by cvs2svn $*/
327
/* Revision 1.1  2007/12/18 18:54:36  sybreon*/
328
/* Partitioned simulation model.*/
329 48 alirezamon
/* */

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