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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_branch_prediction.v] - Blame information for rev 38

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1 38 alirezamon
/******************************************************************************
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 This Source Code Form is subject to the terms of the
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 Open Hardware Description License, v. 1.0. If a copy
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 of the OHDL was not distributed with this file, You
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 can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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 Description: Branch prediction module
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 Generates a predicted flag output and compares that to the real flag
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 when it comes back in the following pipeline stage.
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 Signals are deliberately not named after the pipeline stage they belong to,
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 in order to keep this module generic.
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 Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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 ******************************************************************************/
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`include "mor1kx-defines.v"
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module mor1kx_branch_prediction
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  #(
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    parameter OPTION_OPERAND_WIDTH = 32
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    )
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   (
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    input       clk,
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    input       rst,
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    // Signals belonging to the stage where the branch is predicted.
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    input       op_bf_i,
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    input       op_bnf_i,
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    input [9:0] immjbr_upper_i,
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    output      predicted_flag_o,
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    // Signals belonging to the stage where the branch is resolved.
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    input       prev_op_brcond_i,
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    input       prev_predicted_flag_i,
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    input       flag_i,
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    // Branch misprediction indicator
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    output      branch_mispredict_o
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    );
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   // Compare the real flag with the previously predicted flag and signal a
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   // misprediction in case of a mismatch.
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   assign branch_mispredict_o = prev_op_brcond_i &
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                                (flag_i != prev_predicted_flag_i);
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   // Static branch prediction - backward branches are predicted as taken,
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   // forward branches as not taken.
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   assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
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                             op_bnf_i & !immjbr_upper_i[9];
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endmodule

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