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<h1>drv_eth_vga_capture.v</h1>  </div>
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30
<a href="drv__eth__vga__capture_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001  <span class="keyword">/*</span>
31
<a name="l00002"></a>00002 <span class="keyword">  Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
32
<a name="l00003"></a>00003 <span class="keyword"> </span>
33
<a name="l00004"></a>00004 <span class="keyword">  Redistribution and use in source and binary forms, with or without modification, are</span>
34
<a name="l00005"></a>00005 <span class="keyword">  permitted provided that the following conditions are met:</span>
35
<a name="l00006"></a>00006 <span class="keyword"> </span>
36
<a name="l00007"></a>00007 <span class="keyword">   1. Redistributions of source code must retain the above copyright notice, this list of</span>
37
<a name="l00008"></a>00008 <span class="keyword">      conditions and the following disclaimer.</span>
38
<a name="l00009"></a>00009 <span class="keyword"> </span>
39
<a name="l00010"></a>00010 <span class="keyword">   2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
40
<a name="l00011"></a>00011 <span class="keyword">      of conditions and the following disclaimer in the documentation and/or other materials</span>
41
<a name="l00012"></a>00012 <span class="keyword">      provided with the distribution.</span>
42
<a name="l00013"></a>00013 <span class="keyword"> </span>
43
<a name="l00014"></a>00014 <span class="keyword">  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS&#39;&#39; AND ANY EXPRESS OR IMPLIED</span>
44
<a name="l00015"></a>00015 <span class="keyword">  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
45
<a name="l00016"></a>00016 <span class="keyword">  FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
46
<a name="l00017"></a>00017 <span class="keyword">  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
47
<a name="l00018"></a>00018 <span class="keyword">  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
48
<a name="l00019"></a>00019 <span class="keyword">  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
49
<a name="l00020"></a>00020 <span class="keyword">  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
50
<a name="l00021"></a>00021 <span class="keyword">  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
51
<a name="l00022"></a>00022 <span class="keyword">  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
52
<a name="l00023"></a>00023 <span class="keyword"> */</span>
53
<a name="l00024"></a>00024
54
<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
55
<a name="l00026"></a>00026 <span class="keyword">  \brief DM9000A 10/100 Mbit Ethernet driver for a VGA frame grabber </span>
56
<a name="l00027"></a>00027 <span class="keyword"> */</span>
57
<a name="l00028"></a>00028
58
<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief drv_eth_vga_capture.v</span>
59
<a name="l00030"></a>00030 <span class="keyword">*/</span>
60
<a name="l00031"></a><a class="code" href="classdrv__eth__vga__capture.html">00031</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a>(
61
<a name="l00032"></a>00032     <span class="keyword">//% \name Clock and reset
62
</span>
63
<a name="l00033"></a>00033     <span class="keyword">//% @{</span>
64
<a name="l00034"></a><a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">00034</a>     <span class="vhdlkeyword">input</span>           <a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a>,
65
<a name="l00035"></a><a class="code" href="classdrv__eth__vga__capture.html#a4be6e1a59f945fb87af42e8d7336216a">00035</a>     <span class="vhdlkeyword">input</span>           <a class="code" href="classdrv__eth__vga__capture.html#a4be6e1a59f945fb87af42e8d7336216a">clk_25</a>,
66
<a name="l00036"></a><a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">00036</a>     <span class="vhdlkeyword">input</span>           <a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a>,
67
<a name="l00037"></a>00037     <span class="keyword">//% @}</span>
68
<a name="l00038"></a>00038
69
<a name="l00039"></a>00039     <span class="keyword">//% \name Captured VGA output signals
70
</span>
71
<a name="l00040"></a>00040     <span class="keyword">//% @{</span>
72
<a name="l00041"></a><a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">00041</a>     <span class="vhdlkeyword">input</span>           <a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a>,
73
<a name="l00042"></a><a class="code" href="classdrv__eth__vga__capture.html#a1b7bef5ae7965541b6829e0582237a53">00042</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>]     <a class="code" href="classdrv__eth__vga__capture.html#a1b7bef5ae7965541b6829e0582237a53">vga_r</a>,
74
<a name="l00043"></a><a class="code" href="classdrv__eth__vga__capture.html#a3002998608bbca4b043ef32814a0e90c">00043</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>]     <a class="code" href="classdrv__eth__vga__capture.html#a3002998608bbca4b043ef32814a0e90c">vga_g</a>,
75
<a name="l00044"></a><a class="code" href="classdrv__eth__vga__capture.html#a5c46fd036c0ceb4ca62ee992f3a3f8cd">00044</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>]     <a class="code" href="classdrv__eth__vga__capture.html#a5c46fd036c0ceb4ca62ee992f3a3f8cd">vga_b</a>,
76
<a name="l00045"></a>00045     <span class="keyword">//% @}</span>
77
<a name="l00046"></a>00046
78
<a name="l00047"></a>00047     <span class="keyword">//% \name DM9000A Ethernet hardware interface
79
</span>
80
<a name="l00048"></a>00048     <span class="keyword">//% @{</span>
81
<a name="l00049"></a><a class="code" href="classdrv__eth__vga__capture.html#a84472d11a61abbc3b23a0e969dbf7034">00049</a>     <span class="vhdlkeyword">output</span>          <a class="code" href="classdrv__eth__vga__capture.html#a84472d11a61abbc3b23a0e969dbf7034">enet_clk_25</a>,
82
<a name="l00050"></a><a class="code" href="classdrv__eth__vga__capture.html#ad0ebcebdfa40bfad1f0e1cf767c5f948">00050</a>     <span class="vhdlkeyword">output</span>          <a class="code" href="classdrv__eth__vga__capture.html#ad0ebcebdfa40bfad1f0e1cf767c5f948">enet_reset_n</a>,
83
<a name="l00051"></a><a class="code" href="classdrv__eth__vga__capture.html#acafc6c0c8dba9dc4e5b35d68f9ec30f7">00051</a>     <span class="vhdlkeyword">output</span>          <a class="code" href="classdrv__eth__vga__capture.html#acafc6c0c8dba9dc4e5b35d68f9ec30f7">enet_cs_n</a>,
84
<a name="l00052"></a><a class="code" href="classdrv__eth__vga__capture.html#a21b872000f4cc3cc38086275e5031edb">00052</a>     <span class="vhdlkeyword">input</span>           <a class="code" href="classdrv__eth__vga__capture.html#a21b872000f4cc3cc38086275e5031edb">enet_irq</a>,
85
<a name="l00053"></a>00053
86
<a name="l00054"></a><a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">00054</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span>      <a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a>,
87
<a name="l00055"></a><a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">00055</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span>      <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a>,
88
<a name="l00056"></a><a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">00056</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span>      <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a>,
89
<a name="l00057"></a><a class="code" href="classdrv__eth__vga__capture.html#a01507d79c6d97494ec37aa2d1816c0dc">00057</a>     <span class="vhdlkeyword">inout</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]    <a class="code" href="classdrv__eth__vga__capture.html#a01507d79c6d97494ec37aa2d1816c0dc">enet_data</a>
90
<a name="l00058"></a>00058     <span class="keyword">//% @}</span>
91
<a name="l00059"></a>00059 );
92
<a name="l00060"></a>00060 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__eth__vga__capture.html#a84472d11a61abbc3b23a0e969dbf7034">enet_clk_25</a>  = <a class="code" href="classdrv__eth__vga__capture.html#a4be6e1a59f945fb87af42e8d7336216a">clk_25</a>;
93
<a name="l00061"></a>00061 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__eth__vga__capture.html#ad0ebcebdfa40bfad1f0e1cf767c5f948">enet_reset_n</a> = <a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a>;
94
<a name="l00062"></a>00062 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__eth__vga__capture.html#acafc6c0c8dba9dc4e5b35d68f9ec30f7">enet_cs_n</a>    = <span class="vhdllogic">1&#39;b0</span>;
95
<a name="l00063"></a>00063
96
<a name="l00064"></a><a class="code" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">00064</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">tx_active</a>;
97
<a name="l00065"></a>00065
98
<a name="l00066"></a><a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">00066</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a>;
99
<a name="l00067"></a><a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">00067</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a>;
100
<a name="l00068"></a>00068 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__eth__vga__capture.html#a01507d79c6d97494ec37aa2d1816c0dc">enet_data</a> = (<a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a> == <span class="vhdllogic">1&#39;b1</span>)? <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> : <span class="vhdllogic">16&#39;bZ</span>;
101
<a name="l00069"></a>00069
102
<a name="l00070"></a>00070 <span class="keyword">//************ packet Ethernet and IP/UDP header contents ROM</span>
103
<a name="l00071"></a><a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">00071</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a>;
104
<a name="l00072"></a><a class="code" href="classdrv__eth__vga__capture.html#aa7984493bef70d30c53190e4c148de89">00072</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#aa7984493bef70d30c53190e4c148de89">ram_q</a>;
105
<a name="l00073"></a>00073
106
<a name="l00074"></a><a class="code" href="classdrv__eth__vga__capture.html#a3305dae46003d5c68ca0e917b94aaf4c">00074</a> <a class="code" href="classdrv__eth__vga__capture.html#a3305dae46003d5c68ca0e917b94aaf4c">altsyncram</a> <span class="vhdlchar">ethernet_ram_inst</span>(
107
<a name="l00075"></a>00075     .<span class="vhdlchar">clock0</span>(<a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a>),
108
<a name="l00076"></a>00076     .<span class="vhdlchar">address_a</span>(<a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a>),
109
<a name="l00077"></a>00077     .<span class="vhdlchar">q_a</span>(<a class="code" href="classdrv__eth__vga__capture.html#aa7984493bef70d30c53190e4c148de89">ram_q</a>)
110
<a name="l00078"></a>00078 );
111
<a name="l00079"></a>00079 <span class="vhdlkeyword">defparam</span>
112
<a name="l00080"></a>00080     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">&quot;ROM&quot;</span>,
113
<a name="l00081"></a>00081     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">16</span>,
114
<a name="l00082"></a>00082     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">6</span>,
115
<a name="l00083"></a>00083     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">init_file</span> = <span class="keyword">&quot;drv_eth_vga_capture.mif&quot;</span>;
116
<a name="l00084"></a>00084
117
<a name="l00085"></a>00085 <span class="keyword">//************ vga burst fifo</span>
118
<a name="l00086"></a><a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">00086</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a>;
119
<a name="l00087"></a><a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">00087</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a>;
120
<a name="l00088"></a><a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">00088</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a>;
121
<a name="l00089"></a><a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">00089</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a>;
122
<a name="l00090"></a><a class="code" href="classdrv__eth__vga__capture.html#aba39015d08a3c10b35fba8eb4414d008">00090</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a>) <span class="vhdlkeyword">begin</span>
123
<a name="l00091"></a>00091     <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
124
<a name="l00092"></a>00092         <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> &lt;= <span class="vhdllogic">9&#39;d0</span>;
125
<a name="l00093"></a>00093         <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
126
<a name="l00094"></a>00094         <a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
127
<a name="l00095"></a>00095         <a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
128
<a name="l00096"></a>00096     <span class="vhdlkeyword">end</span>
129
<a name="l00097"></a>00097     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
130
<a name="l00098"></a>00098         <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a>;
131
<a name="l00099"></a>00099
132
<a name="l00100"></a>00100         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a> == <span class="vhdllogic">1&#39;b1</span>)   <a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
133
<a name="l00101"></a>00101         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a> == <span class="vhdllogic">1&#39;b0</span>)                                                  <a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
134
<a name="l00102"></a>00102
135
<a name="l00103"></a>00103         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
136
<a name="l00104"></a>00104             <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> == <span class="vhdllogic">9&#39;d479</span>)   <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> &lt;= <span class="vhdllogic">9&#39;d0</span>;
137
<a name="l00105"></a>00105             <span class="vhdlkeyword">else</span>                            <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> + <span class="vhdllogic">9&#39;d1</span>;
138
<a name="l00106"></a>00106         <span class="vhdlkeyword">end</span>
139
<a name="l00107"></a>00107
140
<a name="l00108"></a>00108         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> == <span class="vhdllogic">9&#39;d479</span>) <a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a> + <span class="vhdllogic">2&#39;d1</span>;
141
<a name="l00109"></a>00109     <span class="vhdlkeyword">end</span>
142
<a name="l00110"></a>00110 <span class="vhdlkeyword">end</span>
143
<a name="l00111"></a>00111
144
<a name="l00112"></a><a class="code" href="classdrv__eth__vga__capture.html#a38a0ce51d1dfba739092251226e2c642">00112</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classdrv__eth__vga__capture.html#a38a0ce51d1dfba739092251226e2c642">fifo_wrreq</a> = (<a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a> == <span class="vhdllogic">1&#39;b1</span> || <a class="code" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span>) &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a> == <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>];
145
<a name="l00113"></a><a class="code" href="classdrv__eth__vga__capture.html#a246788022ac009e7a0ed501c4368fa8d">00113</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classdrv__eth__vga__capture.html#a246788022ac009e7a0ed501c4368fa8d">start_load</a> = <a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a> == <span class="vhdllogic">1&#39;b0</span>;
146
<a name="l00114"></a>00114
147
<a name="l00115"></a><a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">00115</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a>;
148
<a name="l00116"></a><a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">00116</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">11</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>;
149
<a name="l00117"></a>00117
150
<a name="l00118"></a><a class="code" href="classdrv__eth__vga__capture.html#a59768c08add982f9d20148482217c411">00118</a> <a class="code" href="classdrv__eth__vga__capture.html#a59768c08add982f9d20148482217c411">scfifo</a> <span class="vhdlchar">vga_fifo_inst</span>(
151
<a name="l00119"></a>00119     .<span class="vhdlchar">clock</span>(<a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a>),
152
<a name="l00120"></a>00120     .<span class="vhdlchar">data</span>( { <a class="code" href="classdrv__eth__vga__capture.html#a1b7bef5ae7965541b6829e0582237a53">vga_r</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>], <a class="code" href="classdrv__eth__vga__capture.html#a3002998608bbca4b043ef32814a0e90c">vga_g</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>], <a class="code" href="classdrv__eth__vga__capture.html#a5c46fd036c0ceb4ca62ee992f3a3f8cd">vga_b</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>] } ),
153
<a name="l00121"></a>00121     .<span class="vhdlchar">wrreq</span>(<a class="code" href="classdrv__eth__vga__capture.html#a38a0ce51d1dfba739092251226e2c642">fifo_wrreq</a>),
154
<a name="l00122"></a>00122     .<span class="vhdlchar">rdreq</span>(<a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a>),
155
<a name="l00123"></a>00123
156
<a name="l00124"></a>00124     .<span class="vhdlchar">empty</span>(<a class="code" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a>),
157
<a name="l00125"></a>00125     .<span class="vhdlchar">q</span>(<a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>)
158
<a name="l00126"></a>00126 );
159
<a name="l00127"></a>00127 <span class="vhdlkeyword">defparam</span>
160
<a name="l00128"></a>00128     <span class="vhdlchar">vga_fifo_inst</span>.<span class="vhdlchar">lpm_width</span> = <span class="vhdllogic">12</span>,
161
<a name="l00129"></a>00129     <span class="vhdlchar">vga_fifo_inst</span>.<span class="vhdlchar">lpm_numwords</span> = <span class="vhdllogic">1024</span>;
162
<a name="l00130"></a>00130
163
<a name="l00131"></a><a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">00131</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a>;
164
<a name="l00132"></a><a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">00132</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a>;
165
<a name="l00133"></a><a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">00133</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">11</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a>;
166
<a name="l00134"></a>00134
167
<a name="l00135"></a>00135 <span class="keyword">//************</span>
168
<a name="l00136"></a>00136
169
<a name="l00137"></a><a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">00137</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>;
170
<a name="l00138"></a><a class="code" href="classdrv__eth__vga__capture.html#afdf02062e063a6e1eb35038084a33d12">00138</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a>) <span class="vhdlkeyword">begin</span>
171
<a name="l00139"></a>00139     <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
172
<a name="l00140"></a>00140         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>   &lt;= <span class="vhdllogic">16&#39;d0</span>;
173
<a name="l00141"></a>00141         <a class="code" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">tx_active</a>       &lt;= <span class="vhdllogic">1&#39;b0</span>;
174
<a name="l00142"></a>00142
175
<a name="l00143"></a>00143         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a>      &lt;= <span class="vhdllogic">1&#39;b1</span>;
176
<a name="l00144"></a>00144         <a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a>      &lt;= <span class="vhdllogic">1&#39;b1</span>;
177
<a name="l00145"></a>00145         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a>        &lt;= <span class="vhdllogic">1&#39;b0</span>;        <span class="keyword">// low: INDEX, high: DATA</span>
178
<a name="l00146"></a>00146         <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a>    &lt;= <span class="vhdllogic">1&#39;b0</span>;
179
<a name="l00147"></a>00147         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a>   &lt;= <span class="vhdllogic">16&#39;d0</span>;
180
<a name="l00148"></a>00148
181
<a name="l00149"></a>00149         <a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a>        &lt;= <span class="vhdllogic">6&#39;d0</span>;
182
<a name="l00150"></a>00150
183
<a name="l00151"></a>00151         <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a>      &lt;= <span class="vhdllogic">1&#39;b0</span>;
184
<a name="l00152"></a>00152         <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a>     &lt;= <span class="vhdllogic">2&#39;d0</span>;
185
<a name="l00153"></a>00153         <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a>     &lt;= <span class="vhdllogic">12&#39;d0</span>;
186
<a name="l00154"></a>00154     <span class="vhdlkeyword">end</span>
187
<a name="l00155"></a>00155     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50000</span>) <span class="vhdlkeyword">begin</span>
188
<a name="l00156"></a>00156         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
189
<a name="l00157"></a>00157         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
190
<a name="l00158"></a>00158         <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
191
<a name="l00159"></a>00159         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFF</span> }; <span class="keyword">// set IMR(FFh = 0x80)</span>
192
<a name="l00160"></a>00160
193
<a name="l00161"></a>00161         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
194
<a name="l00162"></a>00162     <span class="vhdlkeyword">end</span>
195
<a name="l00163"></a>00163     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50002</span>) <span class="vhdlkeyword">begin</span>
196
<a name="l00164"></a>00164         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
197
<a name="l00165"></a>00165         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
198
<a name="l00166"></a>00166         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h80</span> };
199
<a name="l00167"></a>00167
200
<a name="l00168"></a>00168         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
201
<a name="l00169"></a>00169     <span class="vhdlkeyword">end</span>
202
<a name="l00170"></a>00170     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50005</span>) <span class="vhdlkeyword">begin</span>
203
<a name="l00171"></a>00171         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
204
<a name="l00172"></a>00172         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
205
<a name="l00173"></a>00173         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h1F</span> }; <span class="keyword">// power-up PHY (1Fh = 0x00)</span>
206
<a name="l00174"></a>00174
207
<a name="l00175"></a>00175         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
208
<a name="l00176"></a>00176     <span class="vhdlkeyword">end</span>
209
<a name="l00177"></a>00177     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50007</span>) <span class="vhdlkeyword">begin</span>
210
<a name="l00178"></a>00178         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
211
<a name="l00179"></a>00179         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
212
<a name="l00180"></a>00180         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h00</span> };
213
<a name="l00181"></a>00181
214
<a name="l00182"></a>00182         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
215
<a name="l00183"></a>00183     <span class="vhdlkeyword">end</span>
216
<a name="l00184"></a>00184
217
<a name="l00185"></a>00185     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50010</span>) <span class="vhdlkeyword">begin</span>
218
<a name="l00186"></a>00186         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
219
<a name="l00187"></a>00187         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
220
<a name="l00188"></a>00188         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h31</span> }; <span class="keyword">// set checksum reg (31h = 0x05)</span>
221
<a name="l00189"></a>00189
222
<a name="l00190"></a>00190         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
223
<a name="l00191"></a>00191     <span class="vhdlkeyword">end</span>
224
<a name="l00192"></a>00192     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50012</span>) <span class="vhdlkeyword">begin</span>
225
<a name="l00193"></a>00193         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
226
<a name="l00194"></a>00194         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
227
<a name="l00195"></a>00195         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h05</span> };
228
<a name="l00196"></a>00196
229
<a name="l00197"></a>00197         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
230
<a name="l00198"></a>00198     <span class="vhdlkeyword">end</span>
231
<a name="l00199"></a>00199
232
<a name="l00200"></a>00200
233
<a name="l00201"></a>00201     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50018</span>) <span class="vhdlkeyword">begin</span>
234
<a name="l00202"></a>00202         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
235
<a name="l00203"></a>00203         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
236
<a name="l00204"></a>00204         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hF8</span> }; <span class="keyword">// set MWCMD(F8h = 16-bit data) </span>
237
<a name="l00205"></a>00205
238
<a name="l00206"></a>00206         <a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a> &lt;= <span class="vhdllogic">6&#39;d0</span>;
239
<a name="l00207"></a>00207         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
240
<a name="l00208"></a>00208     <span class="vhdlkeyword">end</span>
241
<a name="l00209"></a>00209     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50020</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d50060</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
242
<a name="l00210"></a>00210         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
243
<a name="l00211"></a>00211         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
244
<a name="l00212"></a>00212         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#aa7984493bef70d30c53190e4c148de89">ram_q</a>;
245
<a name="l00213"></a>00213
246
<a name="l00214"></a>00214         <a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a> + <span class="vhdllogic">6&#39;d1</span>;
247
<a name="l00215"></a>00215         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
248
<a name="l00216"></a>00216     <span class="vhdlkeyword">end</span>
249
<a name="l00217"></a>00217     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50062</span>) <span class="vhdlkeyword">begin</span>
250
<a name="l00218"></a>00218         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a246788022ac009e7a0ed501c4368fa8d">start_load</a> == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
251
<a name="l00219"></a>00219             <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
252
<a name="l00220"></a>00220             <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
253
<a name="l00221"></a>00221             <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">7&#39;d0</span>, <a class="code" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a> };
254
<a name="l00222"></a>00222
255
<a name="l00223"></a>00223             <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
256
<a name="l00224"></a>00224             <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
257
<a name="l00225"></a>00225             <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
258
<a name="l00226"></a>00226         <span class="vhdlkeyword">end</span>
259
<a name="l00227"></a>00227     <span class="vhdlkeyword">end</span>
260
<a name="l00228"></a>00228     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d50063</span>) <span class="vhdlkeyword">begin</span>
261
<a name="l00229"></a>00229         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
262
<a name="l00230"></a>00230         <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
263
<a name="l00231"></a>00231         <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>;
264
<a name="l00232"></a>00232         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
265
<a name="l00233"></a>00233     <span class="vhdlkeyword">end</span>
266
<a name="l00234"></a>00234
267
<a name="l00235"></a>00235
268
<a name="l00236"></a>00236     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
269
<a name="l00237"></a>00237         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
270
<a name="l00238"></a>00238         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
271
<a name="l00239"></a>00239
272
<a name="l00240"></a>00240         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d0</span>)     <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>], <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a> };
273
<a name="l00241"></a>00241         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d1</span>)<a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">4</span>] };
274
<a name="l00242"></a>00242         <span class="vhdlkeyword">else</span>                        <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>, <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] };
275
<a name="l00243"></a>00243
276
<a name="l00244"></a>00244         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d2</span>) <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
277
<a name="l00245"></a>00245         <span class="vhdlkeyword">else</span>                    <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
278
<a name="l00246"></a>00246
279
<a name="l00247"></a>00247         <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> + <span class="vhdllogic">2&#39;d1</span>;
280
<a name="l00248"></a>00248         <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>;
281
<a name="l00249"></a>00249
282
<a name="l00250"></a>00250         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d51022</span>)  <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60016</span> - <span class="vhdllogic">16&#39;d1</span>;
283
<a name="l00251"></a>00251         <span class="vhdlkeyword">else</span>                            <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
284
<a name="l00252"></a>00252     <span class="vhdlkeyword">end</span>
285
<a name="l00253"></a>00253     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d3</span>) <span class="vhdlkeyword">begin</span>
286
<a name="l00254"></a>00254         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
287
<a name="l00255"></a>00255         <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
288
<a name="l00256"></a>00256         <a class="code" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a>;
289
<a name="l00257"></a>00257         <a class="code" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
290
<a name="l00258"></a>00258         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
291
<a name="l00259"></a>00259     <span class="vhdlkeyword">end</span>
292
<a name="l00260"></a>00260     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
293
<a name="l00261"></a>00261         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
294
<a name="l00262"></a>00262         <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
295
<a name="l00263"></a>00263         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
296
<a name="l00264"></a>00264     <span class="vhdlkeyword">end</span>
297
<a name="l00265"></a>00265
298
<a name="l00266"></a>00266
299
<a name="l00267"></a>00267     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60016</span>) <span class="vhdlkeyword">begin</span>
300
<a name="l00268"></a>00268         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
301
<a name="l00269"></a>00269         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
302
<a name="l00270"></a>00270         <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
303
<a name="l00271"></a>00271         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h02</span> }; <span class="keyword">// read TX(02h bit 0 == 0)</span>
304
<a name="l00272"></a>00272
305
<a name="l00273"></a>00273         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
306
<a name="l00274"></a>00274     <span class="vhdlkeyword">end</span>
307
<a name="l00275"></a>00275     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60018</span>) <span class="vhdlkeyword">begin</span>
308
<a name="l00276"></a>00276         <a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
309
<a name="l00277"></a>00277         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
310
<a name="l00278"></a>00278         <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
311
<a name="l00279"></a>00279
312
<a name="l00280"></a>00280         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
313
<a name="l00281"></a>00281     <span class="vhdlkeyword">end</span>
314
<a name="l00282"></a>00282     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60020</span>) <span class="vhdlkeyword">begin</span>
315
<a name="l00283"></a>00283         <a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
316
<a name="l00284"></a>00284         <a class="code" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">tx_active</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a01507d79c6d97494ec37aa2d1816c0dc">enet_data</a>[<span class="vhdllogic">0</span>];
317
<a name="l00285"></a>00285
318
<a name="l00286"></a>00286         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
319
<a name="l00287"></a>00287     <span class="vhdlkeyword">end</span>
320
<a name="l00288"></a>00288     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60022</span>) <span class="vhdlkeyword">begin</span>
321
<a name="l00289"></a>00289         <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">tx_active</a> == <span class="vhdllogic">1&#39;b0</span>)   <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60118</span>;
322
<a name="l00290"></a>00290         <span class="vhdlkeyword">else</span>                    <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60016</span>;
323
<a name="l00291"></a>00291     <span class="vhdlkeyword">end</span>
324
<a name="l00292"></a>00292
325
<a name="l00293"></a>00293     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60118</span>) <span class="vhdlkeyword">begin</span>
326
<a name="l00294"></a>00294         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
327
<a name="l00295"></a>00295         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
328
<a name="l00296"></a>00296         <a class="code" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
329
<a name="l00297"></a>00297         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFC</span> }; <span class="keyword">// set TXPLL(FCh = low byte)</span>
330
<a name="l00298"></a>00298
331
<a name="l00299"></a>00299         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
332
<a name="l00300"></a>00300     <span class="vhdlkeyword">end</span>
333
<a name="l00301"></a>00301     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60120</span>) <span class="vhdlkeyword">begin</span>
334
<a name="l00302"></a>00302         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
335
<a name="l00303"></a>00303         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
336
<a name="l00304"></a>00304         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;hEC</span> };
337
<a name="l00305"></a>00305
338
<a name="l00306"></a>00306         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
339
<a name="l00307"></a>00307     <span class="vhdlkeyword">end</span>
340
<a name="l00308"></a>00308
341
<a name="l00309"></a>00309     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60123</span>) <span class="vhdlkeyword">begin</span>
342
<a name="l00310"></a>00310         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
343
<a name="l00311"></a>00311         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
344
<a name="l00312"></a>00312         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFD</span> }; <span class="keyword">// set TXPLH(FDh = high byte)</span>
345
<a name="l00313"></a>00313
346
<a name="l00314"></a>00314         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
347
<a name="l00315"></a>00315     <span class="vhdlkeyword">end</span>
348
<a name="l00316"></a>00316     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60125</span>) <span class="vhdlkeyword">begin</span>
349
<a name="l00317"></a>00317         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
350
<a name="l00318"></a>00318         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
351
<a name="l00319"></a>00319         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;h03</span> };
352
<a name="l00320"></a>00320
353
<a name="l00321"></a>00321         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
354
<a name="l00322"></a>00322     <span class="vhdlkeyword">end</span>
355
<a name="l00323"></a>00323
356
<a name="l00324"></a>00324     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60128</span>) <span class="vhdlkeyword">begin</span>
357
<a name="l00325"></a>00325         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
358
<a name="l00326"></a>00326         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
359
<a name="l00327"></a>00327         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h02</span> }; <span class="keyword">// write TX(02h = 0x01)</span>
360
<a name="l00328"></a>00328
361
<a name="l00329"></a>00329         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
362
<a name="l00330"></a>00330     <span class="vhdlkeyword">end</span>
363
<a name="l00331"></a>00331     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60130</span>) <span class="vhdlkeyword">begin</span>
364
<a name="l00332"></a>00332         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
365
<a name="l00333"></a>00333         <a class="code" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
366
<a name="l00334"></a>00334         <a class="code" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;h01</span> };
367
<a name="l00335"></a>00335
368
<a name="l00336"></a>00336         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
369
<a name="l00337"></a>00337     <span class="vhdlkeyword">end</span>
370
<a name="l00338"></a>00338
371
<a name="l00339"></a>00339     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> == <span class="vhdllogic">16&#39;d60132</span>) <span class="vhdlkeyword">begin</span>
372
<a name="l00340"></a>00340          <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d50018</span>;
373
<a name="l00341"></a>00341     <span class="vhdlkeyword">end</span>
374
<a name="l00342"></a>00342
375
<a name="l00343"></a>00343     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60132</span>) <span class="vhdlkeyword">begin</span>
376
<a name="l00344"></a>00344         <a class="code" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
377
<a name="l00345"></a>00345         <a class="code" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
378
<a name="l00346"></a>00346         <a class="code" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
379
<a name="l00347"></a>00347         <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> &lt;= <a class="code" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
380
<a name="l00348"></a>00348     <span class="vhdlkeyword">end</span>
381
<a name="l00349"></a>00349
382
<a name="l00350"></a>00350 <span class="vhdlkeyword">end</span>
383
<a name="l00351"></a>00351
384
<a name="l00352"></a>00352 <span class="vhdlkeyword">endmodule</span>
385
</pre></div></div>
386
</div>
387
<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:18 for aoOCS by&#160;
388
<a href="http://www.doxygen.org/index.html">
389
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
390
</body>
391
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